MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 26

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

The MAX11359A contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a SINC
settling time of four output data periods (4 x 200ms).
The MAX11359A has 25% overrange capability built into
the modulator and digital filter:
Figure 4 shows the filter frequency response. The
SINC
times the first notch frequency.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC
repeated at multiples of the first notch frequency. The
SINC
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX11359A
Figure 4. Filter Frequency Response
26
4
4
characteristic -3dB cutoff frequency is 0.228
filter provides an attenuation of better than
-120
-160
-200
-40
-80
0
4
(sinx/x)
0
H f
( ) =
20
⎡
⎢
⎢
⎢
⎢
⎢
⎣
4
N
1
response. The SINC
SIN N
40
FREQUENCY (Hz)
SIN
⎛
⎜
⎝
⎛
⎜
⎝
60
π
π
f
m
f
f
m
f
⎞
⎟
⎠
80
⎞
⎟
⎠
Digital Filtering
⎤
⎥
⎥
⎥
⎥
⎥
⎦
4
100
4
120
filter has a
4
filter are
The MAX11359A incorporates a 10-bit force-sensing
DAC. The DACs reference voltage sets the full-scale
range. Program the DACA_OP register using the serial
interface to set the output voltages of the DAC at OUTA.
Connecting resistors in a voltage-divider configuration
between OUTA, FBA, and GND sets a different closed-
loop gain for the output amplifier (see the Applications
Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 50µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ may degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX11359A features a software-programmable
shutdown mode for the DAC. Power down DACA by
clearing the DAE bits (see the DACA_OP Register sec-
tion). DAC output OUTA goes high impedance when
powered down. The DAC is normally powered down at
power-on reset.
The charge pump provides > 3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DVDD. See Figures 5 and 6 for block diagrams of
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (f
32.768kHz/2), switch resistances (R
the external capacitors (10µF) along with their respec-
tive ESRs, as shown below.
R
OUT
V
RIPPLE
=
f
CLK F
1
V
C
=
DROOP
f
CLK CPOUT
+
2
I
C
OUT
R
=
SWITCH
I
OUT OUT
R
+
+
2
Force-Sense DAC
4
I
OUT
ESR
SWITCH
ESR
Charge Pump
C
F
C
+
Maxim Integrated
CPOUT
ESR
= 5Ω), and
C
CLK
CPOUT
=