MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 27

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MAX11359AETL

Manufacturer Part Number
MAX11359AETL
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX11359AETL

Number Of Channels
10
Architecture
Sigma-Delta
Conversion Rate
10 SPs to 512 SPs
Resolution
16 bit
Input Type
Differential
Interface Type
4-Wire Serial, Microwire, QSPI, SPI
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Power Dissipation
2051.3 mW
Number Of Converters
1
Voltage Reference
1.251 V 1.996 V, 2.422 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX11359AETL+
Manufacturer:
Maxim Integrated Products
Quantity:
135
Figure 5. Linear-Regulator Block Diagram
The MAX11359A provides voltage supervisors to monitor
DVDD and CPOUT. The first supervisor monitors the
DVDD supply voltage. RESET asserts and sets the corre-
sponding LDVD status bit when DVDD falls below the
1.8V threshold voltage. When the DVDD supply voltage
rises above the threshold during power-up, RESET
deasserts after a nominal 1.5s timeout period to give the
crystal oscillator time to stabilize. Set the threshold hys-
teresis using the HYSE bit of the PS_VMONS register.
See the PS_VMONS Register section for configuring hys-
teresis. There is no separate voltage monitor for AVDD,
but the analog supply is covered by the DVDD monitor in
many applications where DVDD and AVDD are externally
connected together. Multiple supply applications where
AVDD and DVDD are not connected together require a
separate external voltage monitor for AVDD. See Figure 7
for a block diagram of the DVDD voltage supervisor.
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
Maxim Integrated
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DVDD
16-Bit Data-Acquisition System with ADC, DAC,
LINEAR 1.65V VOLTAGE REGULATOR
LDOE
1.22V
OP
LDOE
Voltage Supervisors
1.65V
REG
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
AVDD monitor in applications where the charge pump
is disabled and CPOUT is connected to AVDD. AVDD
must be greater or equal to DVDD when CPOUT is
used to monitor AVDD
of the CPOUT voltage supervisor.
The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default, and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
Figure 6. Charge-Pump Block Diagram
REG
M32K
CLOCK GENERATOR
NONOVERLAP
CPE
.
Interrupt Generator (INT)
See Figure 8 for a block diagram
CHARGE-PUMP DOUBLER
MAX11359A
CPOUT
CF-
CF+
27

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