MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 32

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
where g and b are the gain and offset calibration val-
ues, respectively. These calibration values are avail-
able for reading from the TEMP_CAL register.
An internal 1.25V bandgap reference has a buffer with a
selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, resulting
in nominally 1.25V, 2.048V, or 2.5V reference voltage at
REF. The ADC and DAC use this reference voltage. The
state of the internal voltage reference output buffer at
POR is disabled so it can be driven, at REF, with an
external reference between AGND and AVDD. The
MAX11359A reference has an initial tolerance of ±1%.
Program the reference buffer through the serial inter-
face. Bypass REF with a 4.7µF capacitor to AGND.
The MAX11359A includes two op amps. These op amps
feature rail-to-rail outputs, near rail-to-rail inputs, and have
an 80kHz (1nF load) input bandwidth. The DACA_OP
(DACB_OP) register controls the power state of the op
amps. When powered down, the outputs of the op amps
are high impedance.
The MAX11359A provides two uncommitted SPDT switch-
es. Each switch has a typical on-resistance of 35Ω.
Control the switches through the SW_CTRL register, the
PWM output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
MAX11359A
32
Single-Pole/Double-Throw (SPDT) Switches
Operational Amplifiers (Op Amps)
Voltage Reference and Buffer
T
A
= g x T
MEAS
+ b
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX11359A PWM is more
flexible by allowing the UPIO outputs to be driven to
DVDD or regulated CPOUT logic-high voltage levels.
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is avail-
able independent of µC power state. The FLL is typical-
ly disabled in sleep-override mode.
The MAX11359A features a 4-wire serial interface consist-
ing of a chip select (CS), serial clock (SCLK), data in
(DIN), and data out (DOUT). CS must be low to allow data
to be clocked into or out of the device. DOUT is high
impedance while CS is high. The data is clocked in at
DIN on the rising edge of SCLK. Data is clocked out at
DOUT on the falling edge of SCLK. The serial interface is
compatible with SPI modes CPOL = 0, CPHA = 0 and
CPOL = 1, CPHA = 1. A write operation to the
MAX11359A takes effect on the last rising edge of SCLK.
If CS goes high before the complete transfer, the write is
ignored. Every data transfer is initiated by the command
byte. The command byte consists of a start bit (MSB),
R/W bit, and 6 address bits. The start bit must be 1 to
perform data transfers to the device. Zeros clocked in are
ignored. For SPI passthrough mode, see the UPIO_SPI
Register section. An address byte identifies each register.
Table 4 shows the complete register address map for this
family of DAS. Figures 14, 15, and 16 provide timing dia-
grams for read and write commands.
Pulse-Width Modulator (PWM)
Serial Interface
Maxim Integrated