MAX11359AETL Maxim Integrated, MAX11359AETL Datasheet - Page 51

• Manufacturer Part Number: MAX11359AETL
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11359AETL

• Number Of Channels: 10
• Architecture: Sigma-Delta
• Conversion Rate: 10 SPs to 512 SPs
• Resolution: 16 bit
• Input Type: Differential
• Interface Type: 4-Wire Serial, Microwire, QSPI, SPI
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Power Dissipation: 2051.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.251 V 1.996 V, 2.422 V

UPIO_SPI pass-through control register. These bits
map the serial interface signals to the UPIO pins, allow-
ing the DAS to drive other devices at CPOUT or DVDD
voltage levels, depending on the SV_ bit setting found
in the UPIO_CTRL register. Individual bits are provided
to set only the desired UPIO inputs to the SPI pass-
through mode. This mode becomes active when CS is
driven high to complete the write to this register, and
remains active as long as CS stays high (i.e., multiple
pass-through writes are possible). The SPI pass-
through mode is deactivated immediately when CS is
pulled low for the next DAS write.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 19 for an SPI pass-through timing diagram.
UPIO_SPI Register (Power-On State: 0000 XXXX)
Figure 18. SPI Pass-Through Timing Diagram
Maxim Integrated
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO4
UPIO3
UPIO2
UPIO1
DOUT
SCLK
16-Bit Data-Acquisition System with ADC, DAC,
UP4S
DIN
MSB
CS
D
N
D
WRITE TO DAS TO ENABLE SPI MODE
N-1
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
D
UP3S
N-2
D
N-3
D
3
D
2
UP2S
D
1
D
0
E
E
N
N
UP1S
E
E
WRITE THROUGH DAS TO UPIO DEVICE
N-1
N-1
E
E
N-2
N-2
E
E
N-3
N-3
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
through mode is active, and is high (near DVDD or
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
E
E
X
X
3
3
X
E
E
X
X
2
2
X
E
X
E
1
1
E
E
X
X
0
0
D
X
7
D
6
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
MAX11359A
NORMAL WRITE TO DAS
D
5
D
4
X
D
3
D
2
D
1
LSB
D
X
0
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