ispLSI 1024EA-200LT100 Lattice, ispLSI 1024EA-200LT100 Datasheet - Page 11

• Manufacturer Part Number: ispLSI 1024EA-200LT100
• Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE HIGH DENSITY PLD
• Manufacturer: Lattice

Specifications of ispLSI 1024EA-200LT100

• Memory Type: EEPROM
• Number Of Macrocells: 24
• Maximum Operating Frequency: 200 MHz
• Delay Time: 4.5 ns
• Number Of Programmable I/os: 28
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 450
• Supply Current: 152 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
GOE 0/IN 4
GOE 1/IN 5
TDI
TMS
TDO
TCK
RESET
Y0
Y1
Y2
Y3
GND
VCC
VCCIO
NC
2
NAME
1
1
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
91
8
18
68
35
58
17
9
67
60
59
14,
61,
10,
65,
16
1,
24,
38,
51,
74,
87,
NUMBERS
TQFP PIN
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
15,
62,
11,
66,
2,
25,
39,
52,
75,
88,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
36,
89,
40,
85,
12,
26,
49,
63,
76,
99,
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
37,
90
41,
86
13,
27,
50,
64,
77,
100
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
Input - Controls the operation of the ISP state machine.
Output - Functions as an output pin to read serial shift register data.
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
Ground (GND)
Vcc
Supply voltage for output drivers, 5V or 3.3V.
No Connect
11
Specifications ispLSI 1024EA
DESCRIPTION
Table 2-0002A/1024EA