S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 165

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1. Read: Anytime.
1. Read: Anytime.
2.3.87
2.3.88
Freescale Semiconductor
Address 0x036A
Address 0x036B
Write: Anytime.
Write: Anytime.
DDRR
Field
Reset
Reset
7-0
W
W
R
R
Port R data direction—
This register controls the data direction of pins 7 through 0.
The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRR7
RDRR7
Port R Data Direction Register (DDRR)
Port R Reduced Drive Register (RDRR)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
DDRR6
RDRR6
0
0
6
6
Figure 2-86. Port R Reduced Drive Register (RDRR)
Figure 2-85. Port R Data Direction Register (DDRR)
Table 2-83. DDRR Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDRR5
RDRR5
0
0
5
5
DDRR4
RDRR4
NOTE
0
0
4
4
Description
DDRR3
RDRR3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRR2
RDRR2
0
0
2
2
Access: User read/write
Access: User read/write
DDRR1
RDRR1
0
0
1
1
DDRR0
RDRR0
0
0
0
0
165
(1)
(1)