S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 473

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S912XEG128J2MAL

Manufacturer Part Number
S912XEG128J2MAL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEG128J2MAL

Rohs
yes
Core
RISC
Processor Series
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
12 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEG128J2MAL
Manufacturer:
NXP/恩智浦
Quantity:
20 000
11.3.2
This section describes in address order all the S12XECRG registers and their individual bits.
11.3.2.1
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime except if PLLSEL = 1
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
IPLL (no locking and/or insufficient stability).
Freescale Semiconductor
Module Base + 0x0000
Reset
W
R
f VCO
f PLL
f BUS
Register Descriptions
=
=
S12XECRG Synthesizer Register (SYNR)
=
0
7
VCOFRQ[1:0]
Write to this register initializes the lock detector bit.
f
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
f
----------------------------------- -
2 POSTDIV
f PLL
------------ -
VCO
PLL
2 f OSC
×
2
×
f VCO
is same as f
must be within the specified VCO frequency lock range. F.
Table
×
0
6
Figure 11-3. S12XECRG Synthesizer Register (SYNR)
(
------------------------------------ -
(
SYNDIV
REFDIV
11-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
Table 11-2. VCO Clock Frequency Selection
MC9S12XE-Family Reference Manual Rev. 1.25
VCO
VCOCLK Frequency Ranges
80MHz < f
32MHz <= f
48MHz < f
+
+
(divide by one).
1
1
0
5
)
)
Reserved
VCO
VCO
VCO
<= 80MHz
<= 120MHz
<= 48MHz
NOTE
NOTE
0
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
0
3
VCOFRQ[1:0]
SYNDIV[5:0]
00
01
10
11
0
2
BUS
(Bus
0
1
0
0
473

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