LPC11E14FHN33/401, NXP Semiconductors, LPC11E14FHN33/401, Datasheet - Page 25

• Manufacturer Part Number: LPC11E14FHN33/401,
• Description: ARM Microcontrollers - MCU 32kB 4kB EE 10kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11E14FHN33/401,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11E1x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
LPC11E1X
Product data sheet
CAUTION
7.16.6.4 APB interface
7.16.6.5 AHBLite
7.16.6.6 External interrupt inputs
7.17 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Exx user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11E1x is in reset.
To perform boundary scan testing, follow these steps:
Remark: The JTAG interface cannot be used for debug purposes.
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 February 2012
32-bit ARM Cortex-M0 microcontroller
LPC11E1x
© NXP B.V. 2012. All rights reserved.
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