MPC8536ECVTATLA Freescale Semiconductor, MPC8536ECVTATLA Datasheet - Page 110

• Manufacturer Part Number: MPC8536ECVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536ECVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

Electrical Characteristics
Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material
was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease.For system thermal modeling, the chip’s thermal
model without a lid is shown in
of 19.8 W/m•K and a through-plane conductivity of 1.13 W/m•K. The solder balls and air are modeled as a single block
29 x 29 x 0.5 mm with an in-plane conductivity of 0.034 W/m•K and a through plane conductivity of 12.1 W/m•K. The die is
modeled as 9.6 x 9.57 mm with a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed thermal resistance
between the die and substrate assuming a conductivity of 7.5 W/m•K in the thickness dimension of 0.07 mm. The die is centered
on the substrate. The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual
dimensions.
2.24.2
This table shows the chip’s thermal model.
110
Junction-to-ambient (@200 ft/min)
Junction-to-board thermal
Junction-to-case thermal
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
2. Per JEDEC JESD51-2 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
4. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
on the top surface of the board near the package.
(MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 •C/W
Recommended Thermal Model
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Characteristic
Conductivity
Bump/Underfill (9.6 x 9.6 × 0.07 mm) Collapsed Thermal Resistance
Silicon
Table 79. Package Thermal Characteristics (continued)
Figure 72
Kz
Kx
Ky
Kz
Kx
Ky
Kz
The substrate is modeled as a block 29 x 29 x 1.2 mm with an in-plane conductivity
Solder and Air (29 × 29 × 0.5 mm)
Temperature dependent
Substrate (29 × 29 × 1.2 mm)
Table 80. Thermal Model
Die (9.6x9.6 × 0.85 mm)
Value
0.034
0.034
19.8
19.8
1.13
12.1
7.5
Four layer board (2s2p)
JEDEC Board
—
—
Symbol
W/m•K
W/m•K
W/m•K
Units
R
R
R
—
θJA
θJB
θJC
Value
< 0.1
14
10
Freescale Semiconductor
°C/W
°C/W
°C/W
Unit
Notes
C/W
1, 2
3
4