MPC8536ECVTATLA Freescale Semiconductor, MPC8536ECVTATLA Datasheet - Page 42

• Manufacturer Part Number: MPC8536ECVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536ECVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

Electrical Characteristics
Timing diagrams for FIFO appear in the following figures.
42
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
Note:
1. Data valid t
2. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Note:
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency
– Max Hold)
of the speed bins the part belongs to as well as the FIFO mode under operation. See
Restrictions,”
of the speed bins the part belongs to as well as the FIFO mode under operation. See
Restrictions,”
GTX_CLK
TXD[7:0]
TX_EN
TX_ER
FITDV
for more detailed description.
Parameter/Condition
for more detailed description.
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time
Table 26. FIFO Mode Transmit AC Timing Specification (continued)
1
Table 27. FIFO Mode Receive AC Timing Specification
t
FITH
Figure 14. FIFO Transmit AC Timing Diagram
t
FIT
t
FITDV
t
FIRH
Symbol
t
t
t
t
FIRDV
FIRDX
t
t
FIRR
FIRJ
FIRF
FIR
Symbol
/t
t
FIRH
FITDX
t
t
FITR
FITF
1
t
FITDX
Min
6.0
1.5
0.5
45
—
—
—
t
Min
FITF
0.5
—
—
Typ
8.0
50
—
—
—
—
—
Section 2.4.6, “Platform to FIFO
Section 2.4.6, “Platform to FIFO
Typ
—
—
—
t
FITR
Freescale Semiconductor
Max
0.75
0.75
100
250
55
—
—
Max
0.75
0.75
3.0
Unit
Unit
ns
ps
ns
ns
ns
ns
%
ns
ns
ns