MPC8536ECVTATLA Freescale Semiconductor, MPC8536ECVTATLA Datasheet - Page 125

• Manufacturer Part Number: MPC8536ECVTATLA
• Description: Microprocessors - MPU 8536 ENCRYPTED
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536ECVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

6
The following documents are required for a complete description of the chip and are needed to design properly with the part.
7
This table provides a revision history for this hardware specification.
Freescale Semiconductor
Revision
5.
6.
7.
•
•
5
4
3
2
1
0
Capacitors may not be present on all devices
Caution must be taken not to short exposed metal capacitor pads on package top.
All dimensions are symmetric across the package center lines, unless dimensioned otherwise.
MPC8536E PowerQUICC III Integrated Processor Reference Manual (document number: MPC8536ERM)
e500 PowerPC Core Reference Manual (document number: E500CORERM)
Product Documentation
Document Revision History
09/2011
06/2011
11/2010
09/2009
09/2009
08/2009
Date
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Note:
Note: Updated
• Removed PVDD from
• In
• Updated
• In
• In
• Updated
• Updated
• In
• Added Note 6 regarding USB n _DIR pin to
• In
• In
• In
• In
• Updated Die value and Bump/Underfill value in
• In
• In
• In
• Initial public release.
(GPCM)-controlled NOR flash or (FCM) controlled NAND flash, a pullup on LGPL4 is required...”
In addition, updated footnote 26 and added footnote 29 to PCI1_AD.
MDIO/MDC.
UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration.”
LSTSEF to LSTSE for Note 4.
Section 1, “Pin Assignments and Reset
Table
Section 4.3, “Part Numbering,”
Table
Table
Table
Table
Table
Table
Table
Table
FC-PBGA,” and its notes.
1, “Pinout Listing,” updated the power supply for TSEC3 pins to TVDD.
1, “Pinout Listing,” added the following note: “For systems that boot from Local Bus
44, “MII Management DC Electrical Characteristics,” changed the Voh/Vol values for
64, “I2C AC Electrical Specifications,” updated footnote 2.
82, ,
40, “SGMII DC Receiver Electrical Characteristics,” changed LSTSAB to LSTSA and
3, “Recommended Operating Conditions,” for V
5, “Power Dissipation 5,” remove note 5.
5, ”Power Dissipation 5,” changed an “—”’ to “0.”
Table
Table 21
Figure
Figure
Table 85. Document Revision History
Table
56, “eSDHC AC Timing Specifications.”
25, “RGMII and RTBI AC Timing and Multiplexing Diagrams.”
83, ,
81, “Mechanical Dimensions and Bottom Surface Nomenclature of the
Table
Table
1, “Pinout Listing.”
84, added the Revision Level A for Rev 1.2
added an extra bin (1250/500/667) to support DDR3.
Substantive Change(s)
States,”updated the first sentence of the note to say, “The
Table
Table 84
47, “USB General Timing Parameters6.”
DD_CORE,
removed 1.1 ± 55 mV.
Product Documentation
125