XRT91L80ES Exar, XRT91L80ES Datasheet - Page 27

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

xr
xr
xr
xr
REV. 1.0.0
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 10 and Table 6.
F
The parallel interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized
when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is
de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the
delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed
clock. Should the delay exceed this amount, the read and write pointers will point to the same Nibble in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET
signal. The device under the control of the FIFO_AUTORST pin can automatically recover from an overflow
condition. When the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the
3.2
3.3
IGURE
t
t
S
TXPCLKO
TXPCLKO
TX
t
t
S
t
t
TX
TXDI_SU
TXDI_HD
TXPCLKI
TXPCLKI
YMBOL
YMBOL
DUTY
DUTY
TXDI[15:0]P/N
TXPCLKOP/N
10. T
Transmit Parallel Data Input Timing
TXPCLKIP/N
Transmit FIFO
RANSMIT
Transmit parallel clock output period (622.08 MHz non-FEC rate)
Transmit parallel clock output period (666.51 MHz FEC rate)
TXPCLKOP/N Duty Cycle
Transmit parallel clock input period (622.08 MHz non-FEC rate)
Transmit parallel clock input period (666.51 MHz FEC rate)
TXPCLKIP/N "High" to data setup time
TXPCLKIP/N "High" to data hold time
TXPCLKIP/N Duty Cycle
T
ABLE
T
P
ABLE
ARALLEL
6: T
RANSMIT
7: T
RANSMIT
I
NPUT
t
TXDI_SU
P
ARALLEL
T
P
IMING
P
P
ARAMETER
ARAMETER
ARALLEL
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
D
ATA AND
C
t
TXDI_HD
LOCK
19
C
t
TXPCLKO
O
LOCK
UTPUT
I
NPUT
t
TXPCLKI
T
IMING
T
IMING
S
PECIFICATION
S
PECIFICATION
300
300
M
M
40
45
IN
IN
1608
1500
1608
1500
T
T
YP
YP
M
M
60
58
XRT91L80
AX
AX
U
U
NITS
ps
ps
ps
ps
NITS
%
ps
ps
%