XRT91L80ES Exar, XRT91L80ES Datasheet - Page 8

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

TRANSMITTER SECTION
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
HARDWARE COMMON CONTROL
LOOPTM_NOJA
LOOPTM_JA
VCXO_INP
VCXO_INN
TXPCLKIN
TXPCLKIP
REFCLKP
REFCLKN
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
TXOP
TXON
N
N
AME
AME
CMLDIFF
LVCMOS
LVCMOS
LVPECL
LVPECL
LVTTL,
LVTTL,
L
L
LVDS
LVDS
EVEL
EVEL
T
T
YPE
YPE
O
I
I
I
I
I
I
M14
H13
K14
K13
N14
H14
L14
L13
P
J13
J14
P
C6
P2
N6
N4
K1
L1
P6
P4
IN
IN
Loop Timing Mode With Jitter Attenuation
The LOOPTM_JA pin must be set "High" in order to select the
recovered receive clock as the reference source for the de-jitter
PLL.
"Low" = Disabled
"High" = Loop timing with de-jitter PLL Activated
This pin is provided with an internal pull-down.
Loop Timing Mode With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/
32nd of the high-speed recovered receive clock coming from
the CDR.
"Low" = Disabled
"High" = Loop timing Activated
This pin is provided with an internal pull-down.
Transmit Parallel Data Input
The 622.08 Mbps 4-bit parallel transmit data input should be
applied to the transmit parallel bus simultaneously to be sam-
pled at the rising edge of the TXPCLKIP/N input. The 4-bit par-
allel interface is multiplexed into the transmit serial output
interface MSB first (TXDI3P/N).
N
Transmit Parallel Clock Input
622.08 MHz clock input used to sample the 4-bit parallel trans-
mit data input TXDI[3:0]P/N.
N
Transmit Serial Data Output
The transmit serial data output stream is generated by multi-
plexing the 4-bit parallel transmit data input into a 2.488 Gbps
serial data output stream. In Forward Error Correction, the
transmit serial data output stream is 2.666 Gbps.
Reference Clock Input
This differential clock input reference is used for the transmit
clock multiplier unit (CMU) to provide the necessary high-speed
clock reference for this device. Pin ALTFREQSEL determines
the value used as the reference. See Pin ALTFREQSEL for
more details.
Voltage Controled Oscillator Input
This differential clock input is used for the transmit PLL jitter
attenuation. Pin ALTFREQSEL determines the value used as
the reference. See Pin ALTFREQSEL for more details.
OTE
OTE
6
: The XRT91L80 can accept 666.51 Mbps 4-bit parallel
: The XRT91L80 can accept a 666.51 MHz transmit clock
transmit data input for Forward Error Correction (FEC)
Applications.
input for Forward Error Correction (FEC) Applications.
D
D
ESCRIPTION
ESCRIPTION
xr
xr
xr
xr
REV. 1.0.0