XRT91L80ES Exar, XRT91L80ES Datasheet - Page 33

• Manufacturer Part Number: XRT91L80ES
• Description: Bus Transceivers Transceiver
• Manufacturer: Exar

Specifications of XRT91L80ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is
updated on the falling edge of SCLK. The serial data must be applied to the transceiver LSB first. The 16 bits
of serial data are described below.
The first serial bit applied to the transceiver informs the microprocessor that a Read or Write operation is
desired. If the R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set
to “1”, the microprocessor is configured for a Read operation.
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the transceiver first followed by A1 and so forth until all 6 address bits have been
sampled by SCLK.
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data
if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-
dress bits. D0 (LSB) must be sent to the transceiver first followed by D1 and so forth until all 8 data bits have
been sampled by SCLK. Once 16 SCLK cycles have been complete, the transceiver holds the data until CS is
pulled “High” whereby, the serial microprocessor latches the data into the selected internal register.
The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is pro-
vided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The
SDO pin allows the user to read the contents stored in individual registers by providing the desired address on
the SDI pin during the Read cycle.
5.2 16-B
5.3 8-B
5.2.1 R/W (SCLK1)
5.2.2 A[5:0] (SCLK2 - SCLK7)
5.2.3 X (Dummy Bit SCLK8)
5.2.4 D[7:0] (SCLK9 - SCLK16)
IT
IT
S
S
ERIAL
ERIAL
D
D
ATA
ATA
O
I
UTPUT
NPUT
D
D
ESCRITPTION
ESCRIPTION
30
xr
xr
xr
xr
REV. 1.0.0