74LVTH16245BDGG,11 NXP Semiconductors, 74LVTH16245BDGG,11 Datasheet
74LVTH16245BDGG,11
Specifications of 74LVTH16245BDGG,11
Related parts for 74LVTH16245BDGG,11
74LVTH16245BDGG,11 Summary of contents
Page 1
V 16-bit transceiver; 3-state Rev. 10 — 1 March 2012 1. General description The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for V operation at 3 This device is a 16-bit transceiver featuring non-inverting ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +85 C 74LVT16245BDL 74LVTH16245BDL 40 C to +85 C 74LVT16245BDGG 74LVTH16245BDGG 40 C to +85 C 74LVT16245BEV 40 C to +125 C 74LVT16245BBX 74LVTH16245BBX 4. Functional diagram 1DIR 1A0 1A1 1A2 ...
Page 3
... NXP Semiconductors Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 2. IEC logic symbol 74LVT_LVTH16245B Product data sheet 74LVT16245B; 74LVTH16245B 48 1OE G3 1 3EN1 [ BA ] 1DIR 3EN2 [ 2OE 24 6EN4 [ BA ] 2DIR 6EN5 [ 1A0 1A1 5 44 1A2 6 43 1A3 ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LVT16245B 74LVTH16245B 1DIR 1 2 1B0 3 1B1 GND 4 1B2 5 1B3 1B4 1B5 9 GND 10 1B6 11 1B7 12 13 2B0 2B1 14 GND 15 2B2 16 2B3 2B4 2B5 20 GND 21 2B6 22 23 2B7 24 2DIR Fig 3. Pin configuration for SSOP48 and TSSOP48 ...
Page 5
... NXP Semiconductors terminal 1 index area (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however soldered the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SOT1134-2 (HXQFN60) ...
Page 6
... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 1B0 to 1B7 11, 12 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1OE, 2OE 48, 25 2A0 to 2A7 36, 35, 33, 32, 30, 29, ...
Page 7
... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current ...
Page 8
... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C [1] T amb V input clamping voltage IK V HIGH-level output voltage LOW-level output voltage input leakage current I I power-off leakage current V ...
Page 9
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter C off-state input/output io(off) capacitance [1] Typical values are measured at V [2] Unused pins GND. CC [3] This is the bus hold overdrive current required to force the input to the opposite logic state. ...
Page 10
... NXP Semiconductors 11. Waveforms Measurements points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay input (nAn, nBn) to output (nBn, nAn) nOE input nAn or nBn nBn or nAn Measurements points are given in V and V are typical voltage output levels that occur with the output load ...
Page 11
... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 9 ...
Page 12
... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
Page 13
... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 14
... NXP Semiconductors VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions UNIT 1 2 max. 0.3 0.7 0. 0.2 0.6 0.35 OUTLINE VERSION IEC SOT702-1 Fig 11 ...
Page 15
... NXP Semiconductors HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads; 60 terminals; body 0.5 mm terminal 1 index area A10 terminal 1 index area Dimensions Unit max ...
Page 16
... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVT_LVTH16245B v.10 20120301 • Modifications: For type number 74LVT16245BBX and 74LVTH16245BBX the sot code has changed to SOT1134-2 ...
Page 17
... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 18
... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 19
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline ...