M95256-DFDW6TP STMicroelectronics, M95256-DFDW6TP Datasheet - Page 18
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M95256-DFDW6TP
Manufacturer Part Number
M95256-DFDW6TP
Description
EEPROM 256-Kbit serial SPI bus EEPROM
Manufacturer
STMicroelectronics
Datasheet
1.M95256-DFDW6TP.pdf
(53 pages)
Specifications of M95256-DFDW6TP
Rohs
yes
Memory Size
256 Kbit
Organization
32768 x 8 bit
Data Retention
200 yr
Maximum Clock Frequency
20 MHz
Maximum Operating Current
5 mA
Operating Supply Voltage
1.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Interface Type
SPI
Minimum Operating Temperature
- 40 C
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.7 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Instructions
6.2
18/53
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Figure 9.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 12276 Rev 19
High Impedance
0
1
2
Instruction
M95256-W M95256-R M95256-DR M95256-DF
3
4
5
6
7
AI03750D