M24C04-FMC5TG STMicroelectronics, M24C04-FMC5TG Datasheet - Page 13

• Manufacturer Part Number: M24C04-FMC5TG
• Description: EEPROM 4Kbit 100kHz I2C 400 kHZ Fast-Mode
• Manufacturer: STMicroelectronics

Specifications of M24C04-FMC5TG

• Product Category: EEPROM
• Rohs: yes

M24C04-W M24C04-R M24C04-F
5
5.1
Instructions
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in
byte. The device responds to each address byte with an acknowledge bit, and then waits for
the data byte.
Table 3.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle t
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in
A7
W
th
is triggered. A Stop condition at any other time slot does not trigger the internal
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
Address byte
A6
A5
Doc ID 023994 Rev 2
A4
A3
Figure
5, and waits for the address
A2
Figure
6.
A1
Instructions
W
), the
A0
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