M24C04-FMC5TG STMicroelectronics, M24C04-FMC5TG Datasheet - Page 18

• Manufacturer Part Number: M24C04-FMC5TG
• Description: EEPROM 4Kbit 100kHz I2C 400 kHZ Fast-Mode
• Manufacturer: STMicroelectronics

Specifications of M24C04-FMC5TG

• Product Category: EEPROM
• Rohs: yes

Initial delivery state
5.2.1
5.2.2
5.2.3
6
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Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
8) but without sending a Stop condition. Then, the bus master sends another Start
8, without acknowledging the byte.
Figure
Doc ID 023994 Rev 2
8.
M24C04-W M24C04-R M24C04-F