M24C04-FMC5TG STMicroelectronics, M24C04-FMC5TG Datasheet - Page 15

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M24C04-FMC5TG

Manufacturer Part Number
M24C04-FMC5TG
Description
EEPROM 4Kbit 100kHz I2C 400 kHZ Fast-Mode
Manufacturer
STMicroelectronics
Datasheet

Specifications of M24C04-FMC5TG

Product Category
EEPROM
Rohs
yes

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M24C04-W M24C04-R M24C04-F
5.1.2
Page Write
The Page Write mode allows up to bytes to be written in a single Write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits, A8/A4, are the same. If more bytes are sent than will fit up to the end of the
page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same
page, from location 0.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 6.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write
(cont'd)
Figure
Write mode sequences with WC = 1 (data write inhibited)
6. After each transferred byte, the internal page address counter is
NO ACK
Dev select
Dev select
Doc ID 023994 Rev 2
Data in N
R/W
R/W
ACK
ACK
NO ACK
Byte address
Byte address
ACK
ACK
Data in 1
Data in
NO ACK
NO ACK
Data in 2
NO ACK
Data in 3
Instructions
AI02803d
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