M95320-DRMC6TG STMicroelectronics, M95320-DRMC6TG Datasheet - Page 24

• Manufacturer Part Number: M95320-DRMC6TG
• Description: EEPROM 32Kb SPI bus EEPROM 20 MHz 4kB
• Manufacturer: STMicroelectronics

Specifications of M95320-DRMC6TG

• Rohs: yes

Instructions
Note:
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in
24/46
S
C
D
S
C
D
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
if a Write cycle is already in progress,
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
7
32
0
6
33
1
5
34
Data Byte 2
2
4
Instruction
35 36 37 38 39 40 41 42
3
3
4
2
5
1
Table
W
6
0
is internally executed as a sequence of two consecutive
7
Doc ID 5711 Rev 15
7
15
5, the most significant address bits are Don’t Care.
8
6
14 13
9 10
5
Data Byte 3
16-Bit Address
4
43
3
44 45 46 47
3
20 21 22 23 24 25 26 27
2
2
1
1
0
0
7
6
M95320-W M95320-R M95320-DF
6
5
Data Byte N
5
Data Byte 1
4
4
3
3
28 29 30
2
2
1
1
0
0
31
AI01796D