PCA9561D-T NXP Semiconductors, PCA9561D-T Datasheet - Page 9

• Manufacturer Part Number: PCA9561D-T
• Description: EEPROM QUAD 6-BT MULTIPLEX I2C EEPROM
• Manufacturer: NXP Semiconductors

Specifications of PCA9561D-T

• Product Category: EEPROM
• Rohs: yes
• Mounting Style: SMD/SMT
• Package / Case: SOT-163
• Factory Pack Quantity: 2000
• Part # Aliases: PCA9561D,118

NXP Semiconductors
7. Characteristics of the I
PCA9561
Product data sheet
7.1.1 START and STOP conditions
7.1 Bit transfer
The I
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P)
Fig 5.
Fig 6.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The
SDA
SCL
Bit transfer
Definition of START and STOP conditions
(seeFigure
All information provided in this document is subject to legal disclaimers.
START condition
2
SDA
SCL
C-bus
Rev. 4 — 6 November 2012
S
6.)
Quad 6-bit multiplexed I
data valid
data line
stable;
Figure
allowed
change
of data
5).
2
C-bus EEPROM DIP switch
STOP condition
mba607
PCA9561
P
© NXP B.V. 2012. All rights reserved.
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