iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 10

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

sysIO
Buffer Banks
iCE40 devices have up to four I/O banks with independent Vccio rails with an additional configuration bank V
for the SPI I/Os.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec-
tive sysIO buffers and pads. The PIOs are placed on all four sides of the device.
Figure 2-5. I/O Bank and Programmable I/O Cell
The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block.
To save power, the optional iCEgate
within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of
modes along with the necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed inter-
face signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the
data on the positive and negative edges of the system clock signal, creating two data streams.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysIO buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge
of the system clock and then muxed creating one data stream.
Figure 2-6 shows the input/output register block for the PIOs.
VCC
Internal Core
General-Purpose I/O
I/O Bank 2
General-Purpose I/O
I/O Bank 0
VCCIO_2
VCCIO_0
TM
VCC_SPI
latch can selectively freeze the state of individual, non-registered inputs
Bank
SPI
PIO
OUT
IN
OE
IN
2-7
iCEGATE
HOLD
Disabled
OUTCLK
OUTCLK
Enabled
= Statically defined by configuration program
‘1’
‘0’
Programmable Input/Output
INCLK
HD
iCE40 LP/HX Family Data Sheet
I/O Bank 0, 1, 2, or 3
Latch inhibits
switching for
lowest power
Voltage Supply
0 = Hi-Z
1 = Output
GBIN pins optionally
connect directly to an
associated GBUF global
buffer
Enabled
VCCIO
Pull-up
Enable
Pull-up
PAD
Architecture
CC_SPI