iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 8

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

Table 2-3. PLL Signal Descriptions
sysMEM Embedded Block RAM Memory
Larger iCE40 device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4
Kbit in size. This memory can be used for a wide variety of purposes including data buffering, and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic
resources. Each block can be used in a variety of depths and widths as shown in Table 2-4.
Table 2-4. sysMEM Block Configurations
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
SB_RAM512x8
SB_RAM512x8NR
SB_RAM512x8NW
SB_RAM512x8NRNW
SB_RAM1024x4
SB_RAM1024x4NR
SB_RAM1024x4NW
SB_RAM1024x4NRNW
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
SB_RAM2048x2NRNW
1. For iCE40 EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’ and a ‘R’ or ‘W’
REFERENCECLK
BYPASS
EXTFEEDBACK
DYNAMICDELAY[3:0]
LATCHINPUTVALUE
PLLOUTGLOBAL
PLLOUTCORE
LOCK
RESET
depending on the clock that is affected.
Configuration
Signal Name
Block RAM
Direction
Configuration
Output
Output
Output
256x16 (4K)
1024x4 (4K)
2048x2 (4K)
Block RAM
512x8 (4K)
Input
Input
Input
Input
Input
Input
and Size
Input reference clock
When FEEDBACK_PATH is set to SIMPLE, the BYPASS control selects which clock sig-
nal connects to the PLLOUT output.
0 = PLL generated signal
1 = REFERENCECLK
External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set to
EXTERNAL.
Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE is
set to DYNAMIC.
When enabled, forces the PLL into low-power mode; PLL output is held static at the last
input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable.
Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA.
The port has optimal connections to global clock buffers GBUF4 and GBUF5.
Output clock generated by the PLL, drives regular FPGA routing. The frequency gener-
ated on this output is the same as the frequency of the clock signal generated on the
PLLOUTLGOBAL port.
When High, indicates that the PLL output is phase aligned or locked to the input refer-
ence clock.
Active low reset.
WADDR Port
Size (Bits)
11 [10:0]
10 [9:0]
8 [7:0]
9 [8:0]
1
WDATA Port
2-5
Size (Bits)
16 [15:0]
8 [7:0]
4 [3:0]
2 [1:0]
Description
RADDR Port
Size (Bits)
11 [10:0]
10 [9:0]
8 [7:0]
9 [8:0]
iCE40 LP/HX Family Data Sheet
RDATA Port
Size (Bits)
16 [15:0]
8 [7:0]
4 [3:0]
2 [1:0]
Architecture
No Mask Port
No Mask Port
No Mask Port
MASK Port
Size (Bits)
16 [15:0]