iCE40LP1K-CM121 Lattice, iCE40LP1K-CM121 Datasheet - Page 13

• Manufacturer Part Number: iCE40LP1K-CM121
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM121

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-121
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 490

Power On Reset
iCE40 devices have power-on reset circuitry to monitor V
power-up and operation. At power-up, the POR circuitry monitors V
configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after
reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteris-
tics section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to
user functionality once the device has finished configuration.
Programming and Configuration
This section describes the programming and configuration of the iCE40 family.
Device Programming
The NVCM memory can be programmed through the SPI port.
Device Configuration
There are various ways to configure the Configuration RAM (CRAM) including:
1. Internal NVCM Download
2. From a SPI Flash (Master SPI mode)
3. System microprocessor to drive a Serial Slave SPI port (SSPI mode)
The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up
(Warm Boot).
For more details on programming and configuration, see TN1248,
Guide.
Power Saving Options
iCE40 devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra
low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP
and the HX devices operate at 1.2V V
iCE40 devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power
requirements of their applications. While these features are available in both device types, these features are
mainly intended for use with iCE40 LP devices to manage power consumption.
Table 2-9. iCE40 Power Saving Features Description
PLL
iCEGate
Device Subsystem
When LATCHINPUTVALUE is enabled, forces the PLL into low-power mode; PLL output held static
at last input clock value.
To save power, the optional iCEgate latch can selectively freeze the state of individual, non-regis-
tered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or
clock-enable control.
CC
.
2-10
CC
Feature Description
, V
CCIO_2
iCE40 Programming and Configuration Usage
CC
, V
, V
PP_2V5
iCE40 LP/HX Family Data Sheet
CCIO_2
, and V
, V
PP_2V5
CC_SPI
, and V
voltage levels during
Architecture
CC_SPI
(controls