1894KI-32LFT IDT, 1894KI-32LFT Datasheet - Page 28

• Manufacturer Part Number: 1894KI-32LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894KI-32LFT

• Rohs: yes
• Part # Aliases: ICS1894KI-32LFT

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Register
Register
25.15:12
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
25.11
25.10
25.9
25.8
25.7
25.6
25.5
25.4
25.3
25.2
25.1
25.0
Bit
Note 1:
Note 2:
Note 3:
‡ Whenever the PHY address is equal to 00000 (binary), the Isolate bit 0.10 is logic one, whenever the PHY address Is not equal to 00000, the
Isolate bit 0.10 is logic zero.
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits.
25 - Extended Control Register
26 - 31 - Extended Control Register (Reserved)
TX100BIAS_SET
TX10BIAS_SET
OUTDLY_CTL
Ignored if Auto negotiation is enabled.
CW = Command Override Write
LH = Latching High
LL = Latching Low
LMX = Latching Maximum
RO = Read Only
RW = Read/Write
RW/0 = Read/Write Zero
RW/1 = Read/Write One
SC = Self-clearing
SF = Special Functions
L = Latched on power-up/hardware reset
Definition
Reserved
Reserved
Reserved
Reserved
Reserved
The normal output current of the Bias block for
10BaseT is 540uA. Changing the register can modify
the current with a step size of 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
The normal output current of the Bias block for
100BaseTX is 180uA. Changing the register can
modify the current with a step size of 5%
000: output 80% current
001: output 85% current
010: output 90% current
011: output 95% current
100: output 100% current
101: output 105% current
110: output 110% current
111: output 115% current
This register controls the delay time of the digital
control signal for xmit_dac.
00: Longest delay time (same as original design)
01: Long delay time
10: Short delay time
11: Shortest delay time
Reserved
Reserved
Reserved
When Bit = 0
When Bit = 1
28
Access
RW
RW
RW
RW
RW
RW
RW
2
SF
ICS1894-32
2
Default
0
0
1
1
0
0
1
0
0
0
0
1
PHYCEIVER
3
REV M 021512
Hex
0
6
4
1