1894KI-32LFT IDT, 1894KI-32LFT Datasheet - Page 3

• Manufacturer Part Number: 1894KI-32LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894KI-32LFT

• Rohs: yes
• Part # Aliases: ICS1894KI-32LFT

Pin Descriptions
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Number
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
AMDIX/RXD3
RMII/RXDV
RESET_N
P3/RXD2
REFOUT
SPEED/
ANSEL/
RXCLK
TP_AN
TP_BN
RXTRI/
TXCLK
TP_AP
TP_BP
P2/INT
VDDIO
Name
REFIN
FDPX/
RXER
VDDD
TCSR
MDIO
RXD1
RXD0
TXEN
NOD/
TXD0
TXD1
TXD3
TXT2
MDC
VDD
VDD
VSS
VSS
Pin
Ground Connect to ground.
Ground Connect to ground.
Type
Output 25 MHz crystal output, floating in RMII mode
Power
Power
Power
Power
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
Input
Input
Input
Input
Input
Input
Input
Input
Pin
AIO
AIO
AIO
AIO
AIO
IO
1
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).
Hardware reset for the entire chip (active low)
PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
AMDIX enable as input (during power on reset/hardware reset)
Receive data Bit 3 in MII mode as output.
PHY address Bit 3 as input (during power on reset/hardware reset)
Receive data Bit 2 in MII mode as output.
RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in both RMII and MII mode as output.
Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in both RMII and MII mode as output
RMII/MII select as input (during power on reset/hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output.
3.3 V/1.8 V IO Power Supply.
Auto-negotiation enable as input (during power on reset/hardware reset)
Receive clock in MII mode as output.
Node select as input (during power on reset/hardware reset)
Receive error in MII/RMII mode as output
It is recommended to always pull this pin low on power-up or hardware reset.
10M/100M select as input (during power on reset/hardware reset)
Transmit clock in MII mode as output
Transmit enable in RMII/MII mode
Transmit data Bit 0 in RMII/MII mode
3.3 V Power Supply
Transmit data Bit 1 in RMII/MII mode
Transmit data Bit 2 in MII mode
Transmit data Bit 3 in MII mode
25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.
Pin Description
3
ICS1894-32
PHYCEIVER
REV M 021512