1894KI-32LFT IDT, 1894KI-32LFT Datasheet - Page 4

• Manufacturer Part Number: 1894KI-32LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894KI-32LFT

• Rohs: yes
• Part # Aliases: ICS1894KI-32LFT

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Number
PADDLE
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
31
32
Notes:
1. AIO: Analog input/output PAD.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
asserted, two bits of recovered data are sent from the PHY to the MAC.
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
asserted, two bits of data are received by the PHY from the MAC.
P1/ISO/LED1
P0/LED0
Name
VSS
Pin
Ground Connect to ground.
Type
Pin
IO
IO
1
PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0
(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1
(function configurable, default is "10/100 mode") as output; After latch, alternates as
a real time receiver isolation input.
Pin Description
4
ICS1894-32
PHYCEIVER
REV M 021512