S25FL128SDPMFIG11 Spansion, S25FL128SDPMFIG11 Datasheet - Page 106

• Manufacturer Part Number: S25FL128SDPMFIG11
• Description: Flash 128Mb 3V 66MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SDPMFIG11

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: Flash
• Memory Size: 128 Mbit
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 100 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

106
SCLK
SCLK
SCLK
CS#
CS#
IO0
IO1
CS#
IO0
IO1
IO0
IO1
0
7
0
7
Figure 10.47 Continuous DDR Dual I/O Read Subsequent Access (4-byte Address, EHPLC= 01b)
30
31
0
1
6
1
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4
device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See
Registers on page 65
32b Add
6
8 cycles
22
22
Figure 10.48 DDR Dual I/O Read (4-byte Address, BEh or BDh [ExtAdd=1], HPLC=00b)
2
5
2
3
2
5
8
0
1
3
Instruction
4
8 cycles
Instruction
3
4
8 cycles
6
7
4
3
9
(4-byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b)
4
3
2 cycles
4
5
Mode
Figure 10.46 DDR Dual I/O Read Initial Access
5
for more details.
2
5
2
3
2
10
6
1
0
1
6
1
S25FL128S and S25FL256S
7
0
11
7
0
31
30
8
31
8 cycles
32b Add
30
22
22
8
7
7
32b Add
8 cycles
2
3
12
15
D a t a
2
3
0
1
6
6
5 cycles Dummy
15
Optional DLP
6
7
0
1
16
2 cycles
5
5
Mode
4
5
13
16
S h e e t
2
3
17
4
4
0
1
17
3
3
18
14
18
Section 8.5.11, SPI DDR Data Learning
2
2
6 cycles
7
7
Dummy
19
5 cycles Dummy
6
6
Optional DLP
1
1
19
S25FL128S_256S_00_05 July 12, 2012
8
5
5
20
0
0
4
4
20
3
3
21
6
7
15
2
2
per data
2 cycles
21
1
1
4
5
22
0
0
6
7
2
3
22
6
7
16
2 cycles
per data
23
4
5
per data
2 cycles
4
5
0
1
2
3
23
2
3
24
0
1
6
7
0
1
17
6
7
6
7
24
25
2