S34ML01G200TFI003 Spansion, S34ML01G200TFI003 Datasheet
S34ML01G200TFI003
Specifications of S34ML01G200TFI003
Related parts for S34ML01G200TFI003
S34ML01G200TFI003 Summary of contents
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... Gb Densities: 4-bit ECC, x8 I/O and 3V V S34ML01G2, S34ML02G2, S34ML04G2 Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See ...
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... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...
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... Publication Number S34ML01G2_04G2 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. ...
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... Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6. Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Command Latch Cycle 6.2 Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 Data Input Cycle Timing Spansion ® SLC NAND Flash Memory for Embedded S34ML01G2_04G2_01 August 3, 2012 ...
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... Physical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8. System Interface Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.1 System Bad Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 Bad Block Management 10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 August 3, 2012 S34ML01G2_04G2_01 ( ® Spansion SLC NAND Flash Memory for Embedded 5 ...
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... VBM063 — 63-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 8.1 Program Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 8.2 Read Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6 Spansion ® SLC NAND Flash Memory for Embedded ...
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... Figure 8.3 Page Programming Within a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 9.1 Bad Block Replacement Figure 9.2 Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 August 3, 2012 S34ML01G2_04G2_01 ( ® Spansion SLC NAND Flash Memory for Embedded 7 ...
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... DC Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz Table 5.7 Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9.1 Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 Spansion ® SLC NAND Flash Memory for Embedded S34ML01G2_04G2_01 August 3, 2012 ...
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... Serial number (unique identifier), which allows the devices to be uniquely identified. Read ID2 extension. These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the data sheet. For more details about them, contact your nearest Spansion sales office. August 3, 2012 S34ML01G2_04G2_01 ( ® ...
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... Device S34ML01G2 S34ML02G2 S34ML04G2 1.1 Logic Diagram 10 Spansion Density (bits) Main Spare 128M 256M 512M x 8 16M x 8 Figure 1.1 Logic Diagram VCC CE# WE# RE# ALE CLE WP# VSS Table 1.1 Signal Names I/O7 - I/O0 CLE ...
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... I/O2 I/O3 I/O4 I/ ® Spansion SLC NAND Flash Memory for Embedded VSS ( I/O7 I/O6 I/O5 I/O4 NC VCC (1) NC VCC VSS NC VCC (1) NC I/O3 I/O2 I/O1 I/ VSS (1) A9 A10 B10 RB# ...
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... The PCB track widths must be sufficient to carry the currents required during program and erase operations internal voltage detector disables all functions whenever V during power transitions. 12 Spansion Table 1.2 Pin Description Description after the falling edge of RE# which also increments the internal column address counter by one ...
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... Register Data Register Figure 1.5 Array Organization Plane( 1022 1023 I/O [7:0] 2048 bytes spare bytes Array Organization(x8) ® Spansion SLC NAND Flash Memory for Embedded PAGE Buffer Y Decoder I/O Buffer I/O0~I/O7 1 Page = (2k + spare) bytes 1 Block = (2k + spare) bytes x 64 pages = (128k + spare) bytes ...
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... A0 - A11: column address in the page A12 - A17: page address in the block A18: plane address (for multiplane operations) / block address (for normal operations) A19 - A28: block address 14 Spansion Table 1.3 Address Cycle Map — Device ...
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... Low High Command Input High Low Address Input Low High Low Low Low Low ® Spansion SLC NAND Flash Memory for Embedded I/O4 I/O5 I/O6 I/ (1) L (1) L (1) L (1) A16 A17 A18 A19 A24 A25 A26 ...
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... The Write Protect pin is not latched by Write Enable to ensure the protection even during power up. 2.6 Standby In Standby, the device is deselected, outputs are disabled, and power consumption is reduced. 16 Spansion Table 1.6.) Figure 6 ...
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... ECh 29h-17h-04h-19h ® Spansion SLC NAND Flash Memory for Embedded Acceptable Supported on 4th Cycle Command S34ML01G2 during Busy No Yes No Yes No Yes No Yes 10h No No 10h ...
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... The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number indicated in within a block. 18 Spansion The system controller may detect the completion analyzing the output of the R/B pin ...
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... In case of failure in any of 1st and 2nd page program, the fail bit of the Status Section 3.9 on page 21 for further info. Table 5.7 on page 37. In addition, pages must be programmed sequentially details the sequence. ® Spansion SLC NAND Flash Memory for Embedded ). Once it has become ready again, the ‘81h’ 19 ...
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... Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to a destination page of the same plane. 20 Spansion and Figure 6 ...
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... PASS for specific Status Register definition, and to Status Register Bit Bit 0, Pass/Fail Bit 1, Cache Pass/Fail defines the Read Status Enhanced behavior and timings. The plane and die address ® Spansion SLC NAND Flash Memory for Embedded Section 3.6 and Section 3.6 and Section 3.7 Figure 6 ...
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... Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output time of one page exceeds random access time (t of the next page is hidden by data downloading of the previous page. 22 Spansion Table 3 ...
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... I/O5 must be polled to find out if the last programming is finished before starting any other operation. See details. August 3, 2012 S34ML01G2_04G2_01 ( Table 3.2 on page 22 ® Spansion SLC NAND Flash Memory for Embedded Figure 6.30 on page 52). This and Figure 6.31 on page 53 for more 23 ...
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... If the target pattern for the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input cycle, as described in Figure 3.1. 24 Spansion DBSY for more details ...
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... Din tADL Page N ADDR ADDR ADDR Din Din tADL Page M ® Spansion SLC NAND Flash Memory for Embedded Din Din Din CMD 10h tWB tPROG ADDR ADDR CMD 10h R1 R2 tWB tPROG Page M Figure 3.2. ...
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... S34ML04G2 Data Internal Chip Number Cell type Number of simultaneously programmed pages Interleave program Between multiple chips Cache Program 26 Spansion shows the operation sequence, while Table 3.3 Read ID for Supported Configurations V 1st 2nd CC 3.3V 01h F1h 3 ...
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... Reserved Description I/O7 I/ 128 kB 256 kB 512 Reserved 0 Reserved ® Spansion SLC NAND Flash Memory for Embedded I/O5 I/O4 I/O3 I/O2 I/O1 I/ I/O5 I/O4 I/O3 I/O2 I/O1 I/ ...
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... ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. 28 Spansion Description ...
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... Get Features and Set Features supports Read Cache commands supports Page Cache Program command Manufacturer information Block Memory Organization Block ® Spansion SLC NAND Flash Memory for Embedded Table 3.9 Values 4Fh, 4Eh, 46h, 49h 02h, 00h S34ML01G2: 14h, 00h S34ML02G2: 1Ch, 00h ...
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... R 139-140 M t CCS 141-163 Reserved (0) 164-165 M Vendor specific Revision number 166-253 Vendor specific 30 Spansion Table 3.9 Parameter Page Description (Sheet Description 4-7 Column address cycles 0-3 Row address cycles 5-7 Reserved partial page layout is partial page data followed by ...
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... Figure 6.39 on page and V on the other hand) are shorted together at all times. SSQ Figure 6.39 on page 58. The two-step command sequence for ® Spansion SLC NAND Flash Memory for Embedded Values S34ML01G2: 56h, 3Eh S34ML02G2: FEh, A4h S34ML04G2: 80h, EFh Repeat Value of bytes 0-255 ...
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... Vcc GND Rp value guidence Rp (min. 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B# pin. L Rp(max) is determined by maximum permissible limit of tr. 32 Spansion Figure 4.1. Figure 4.1 Ready/Busy Pin Electrical Application Rp ibusy Ready V ...
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... (similarly to Figure 6.26 on page 51). At the end of this time, the command RST Table 3.2 on page 22 Figure 6.40 and Figure 6.41 on page WE# I/O[7:0] Valid WP# > 100 ns ® Spansion SLC NAND Flash Memory for Embedded for more information on device status. ns prior to raising the WE# pin WW 59. Sequence Aborted 33 ...
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... Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions. 5.3 AC Test Conditions Parameter Input pulse levels Input rise and fall times Input and output timing levels Output load (2.7V - 3.6V) 34 Spansion Table 5.1 Valid Blocks Symbol Min S34ML01G2 Device N ...
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... REH t RHOH t RHW t RHZ t RLOH RST WHR t WHR2 ® Spansion SLC NAND Flash Memory for Embedded Min Max Unit 10 — — — — — — ns — — — ...
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... Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more details. 5.6 Pin Capacitance Parameter Input Input / Output 36 Spansion Table 5.5 DC Characteristics and Operating Conditions Symbol Test Conditions Power up Current I ...
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... Table 5.7 Program / Erase Characteristics Parameter (2) Main + Spare Array ) specification. Copy Back Program may not meet this specification when copying from an odd PROG ® Spansion SLC NAND Flash Memory for Embedded Description Min Typ Max Unit t — ...
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... Write Enable. Moreover for commands that starts a modify operation (write/ erase) the Write Protect pin must be high. CLE CE# WE# ALE I/Ox 38 Spansion Figure 6.1 Command Latch Cycle tCLS tCLH tCS tCH ...
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... Add1 Add2 Figure 6.3 Input Data Latch Cycle tWC tALS tWP tWP tWH tWH tDH tDH tDS tDS Din Din 0 ® Spansion SLC NAND Flash Memory for Embedded tWC tWC tWP tWH tWH tALH tALS tALH tALS tALH tDH tDH tDH tDS ...
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... This parameter is sampled and not 100% tested valid when frequency is higher than 33 MHz. RLOH 4. t starts to be valid when frequency is lower than 33 MHz. RHOH 40 Spansion Figure 6.4 Data Output Cycle Timing tRC tREH tREA ...
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... Figure 6.7 Page Read Operation Intercepted by CE# tWB Row Col. Col. Row Row 30h Add. 2 Add. 1 Add. 2 Add. 3 Add. 1 Column Address Row Address ® Spansion SLC NAND Flash Memory for Embedded tCLR tCSD tAR tR tRC tRHZ tRR Dout Dout Dout Busy tCLR ...
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... Input Command Column Address R/B# Note the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. ADL 42 Spansion Figure 6.8 Page Read Operation Timing with CE# Don’t Care tRR Dout Col ...
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... Row Din Din 85h M Add1 Add2 Add1 Add2 Add3 N Random Data Column Address Column Address Input Command ® Spansion SLC NAND Flash Memory for Embedded CE# don’t care Din Din Din Din Don’t Care tADL tWHR tWB tPROG Col ...
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... Column Address Page Row Address Input Command R/B# Ex.) Two-Plane Page Program R/B# I/O0~7 80h Note: 1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh. 44 Spansion Figure 6.12 Random Data Output tWB tAR tRC tR tRR Col ...
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... Figure 6.15 Block Erase Operation (Erase One Block) tWB D0h Row Add1 Row Add2 Row Add3 Row Address BUSY Erase Command ® Spansion SLC NAND Flash Memory for Embedded DIN CMD DIN DIN DIN ... Dn 11h tADL ...
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... R1A-R3A Row address for block on plane 0. R1A is the least significant byte. 2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte. 3. Same restrictions on address of blocks on plane 0(A) and 1(B) and allowed commands as 46 Spansion Figure 6.16 Multiplane Block Erase ...
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... Busy time) Busy Source Target 35h 85h Data Add Inputs Copy Back Code tR (Read Busy time) Busy ® Spansion SLC NAND Flash Memory for Embedded Target SR0 10h 70h Add Inputs Read Status Register tPROG (Program Busy time) Busy Target 10h 70h ...
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... Data Field Notes: 1. Copy Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh. 48 Spansion Figure 6.20 Multiplane Copy Back Program tR 35h 00h Add ...
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... IPBSY Figure 6.22 Read Status Cycle t CLR tCLS t CLH WHR 70h ® Spansion SLC NAND Flash Memory for Embedded C2 85h 10h PROG Figure 6.14 apply CEA CHZ t COH t RHZ t ...
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... ALE RE# I/O0-7 78h 6.20 Read Status Timing CLE WE# ALE RE# 70h I/O0-7 CLE WE# ALE RE# I/O0-7 78h 50 Spansion Figure 6.23 Read Status Enhanced Cycle Figure 6.24 Read Status Timing tWHR SR tREA Figure 6.25 Read Status Enhanced Timing tWHR tAR ® ...
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... Page N Page Page N Page Page Page ® Spansion SLC NAND Flash Memory for Embedded tWB tRC tRC tRR Dout Dout Dout Dout 31h Dout Page Address Page Address M Col ...
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... CMD I/Ox 30h tWB SR[6] A CMD Cycle Type I/Ox 00h SR[6] As defined for Read Cache (Sequential or Random) CMD Cycle Type I/Ox 31h SR[6] 52 Spansion CMD Dout 31h h D tWB tWB tRR tCBSYR tR CMD ADDR ADDR ADDR ADDR Page N 00h ...
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... Col. Col. Row. Row. Row. Din Din 10h N M Add1 Add2 Add2 Add3 Add1 Column Address Row Address ® Spansion SLC NAND Flash Memory for Embedded tWC Col. Col. Row. Row. Row. Din Din 15h N M Add1 Add2 Add1 Add2 Add3 ...
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... Col. I/Ox 80h Add1 Column Address R/B# 1 Note: 1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used. 54 Spansion Figure 6.32 Multiplane Cache Program 11h Data Input t DBSY Return to 1 Repeat a max of 63 times ...
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... Row Din Din 80h 11h N Add2 Add1 Add2 Add3 M Row Address tDBSY ® Spansion SLC NAND Flash Memory for Embedded Address Input Data Input 15h A13~A17:Valid A18:Fixed”Low” A19~A31:Fixed”Low” t PCBSY Address Input Data Input 10h A13~A17:Valid A18:Fixed”Low” ...
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... Read ID2 Commands Note: 1. 4-cycle address is shown for the S34ML01G2. For S34ML02G2 and S34ML04G2, insert an additional address cycle of 00h. 56 Spansion Figure 6.34 Read ID Operation Timing tWHR ...
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... August 3, 2012 S34ML01G2_04G2_01 ( Figure 6.36 ONFI Signature Timing t WHR 20h 4Fh 4Eh tREA Figure 6.37 Read Parameter Page Timing 00h ® Spansion SLC NAND Flash Memory for Embedded 46h 49h ... ... ...
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... 100 µs max Invalid Ready/Busy Note 1.8 Volt for 3.0V supply devices Spansion Figure 6.38 OTP Entry Timing 04h 19h Figure 6.39 Power On and Data Protection Timing max Operation ® ...
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... WP# R/B# August 3, 2012 S34ML01G2_04G2_01 ( Figure 6.40 Program Enabling / Disabling Through WP# Handling WE# 10h I/Ox WP# R/B# Figure 6.41 Erase Enabling / Disabling Through WP# Handling WE# D0h I/Ox WP# R/B# ® Spansion SLC NAND Flash Memory for Embedded t WW 80h 10h t WW 60h D0h 59 ...
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... D 19.80 D1 18.30 E 11. 0.50 Θ 0˚ Spansion NOTES: TS/TSR 48 MO-142 ( CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982) NOM MAX 2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). --- 1.20 3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK. ...
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... SOLDER BALL PLACEMENT SOLDER BALL PLACEMENT 9 DEPOPULATED SOLDER BALLS ® Spansion SLC NAND Flash Memory for Embedded ASME Y14.5M-1994. SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION " ...
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... CE# WE# ALE I/ CLE CE# RE# ALE R/B# WE# I/ Spansion Figure 8.1 Program Operation with CE# Don't Care Cycle) Figure 8.2 Read Operation with CE# Don't Care If sequential row read enabled, CE must be held low during tR. ...
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... August 3, 2012 S34ML01G2_04G2_01 ( Figure 8.3 Page Programming Within a Block (64) (32) (3) (2) (1) Data Register DATA IN : Data (1) Data (64) ® Spansion SLC NAND Flash Memory for Embedded (64) Page 63 (1) Page 31 (3) Page 2 (32) Page 1 (1) Page 0 Data Register Ex ...
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... Data in Block A is copied to same location in Block B, which is valid block. 3. Nth page of block A, which is in controller buffer memory, is copied into Nth page of Block B. 4. Bad block table should be updated to prevent from erasing or programming Block A. 64 Spansion Table 9 ...
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... Figure 9.2 Bad Block Management Flowchart Start Block Address= Block 0 No Update Data (1) Bad Block Table =FFh? Yes No Last Block? Yes End ® Spansion SLC NAND Flash Memory for Embedded Increment Block Address 65 ...
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... Bus Width Technology 2 = Density 01G = 02G = 04G = Device Family S34ML Spansion SLC NAND Flash Memory for Embedded Valid Combinations Bus Package Temperature Technology Width Type Range 2 00 ® SLC NAND Flash Memory for Embedded Tray 13” ...
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... 11. Revision History Section Revision 01 (August 3, 2012) Initial release August 3, 2012 S34ML01G2_04G2_01 ( Description ® Spansion SLC NAND Flash Memory for Embedded 67 ...
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... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...