PCAL6416AHF,128 NXP Semiconductors, PCAL6416AHF,128 Datasheet - Page 16

• Manufacturer Part Number: PCAL6416AHF,128
• Description: Interface - I/O Expanders 16-bit I2C-busSMBus Low Voltage
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416AHF,128

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders

NXP Semiconductors
PCAL6416A
Product data sheet
7.4.10 Interrupt status register pair (4Ch, 4Dh)
7.4.11 Output port configuration register (4Fh)
7.5 I/O port
These read-only registers are used to identify the source of an interrupt. When read, a
logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0
indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register pair write operation is described in
register pair read operation is described in
Table 27.
Table 28.
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence is to program this register (4Fh) before the configuration register
(06h and 07h) sets the port pins as outputs.
ODEN0 configures Port 0_x and ODEN1 configures Port 1_x.
Table 29.
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
recommended levels for proper operation.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
DD(P)
Interrupt status port 0 register (address 4Ch) bit description
Interrupt status port 1 register (address 4Dh) bit description
Output port configuration register (address 4Fh)
S0.7
S1.7
or V
7
0
7
0
7
0
All information provided in this document is subject to legal disclaimers.
SS
. The external voltage applied to this I/O pin should not exceed the
Rev. 3 — 24 December 2012
S0.6
S1.6
6
0
6
0
6
0
Low-voltage translating 16-bit I
S0.5
S1.5
5
0
5
0
5
0
reserved
S0.4
S1.4
Section
4
0
4
0
4
0
8.2.
S0.3
S1.3
3
0
3
0
3
0
2
C-bus/SMBus I/O expander
S0.2
S1.2
PCAL6416A
2
0
2
0
2
0
DD(P)
Figure
to a maximum of
ODEN1
© NXP B.V. 2012. All rights reserved.
S0.1
S1.1
Section
1
0
1
0
1
0
10). A logic 1
ODEN0
8.1. A
S0.0
S1.0
16 of 54
0
0
0
0
0
0