PCA9538APWJ NXP Semiconductors, PCA9538APWJ Datasheet
PCA9538APWJ
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PCA9538APWJ Summary of contents
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PCA9538A Low-voltage 8-bit I Rev. 1 — 28 September 2012 1. General description The PCA9538A is a low-voltage 8-bit General Purpose Input/Output (GPIO) expander with interrupt and reset for I simple solution when additional I/Os are needed while keeping interconnections ...
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... Table 1. Ordering information Type number Topside mark PCA9538ABS P3A PCA9538APW PA9538A 3.1 Ordering options Table 2. Ordering options Type number Orderable part number PCA9538ABS PCA9538ABSHP PCA9538APW PCA9538APWJ PCA9538A Product data sheet Low-voltage 8-bit 0.10 V (typical) hys DD 2 C-bus Package Name Description HVQFN16 plastic thermal enhanced very thin quad flat package ...
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... NXP Semiconductors 4. Block diagram A0 A1 SCL SDA V DD RESET V SS Fig 1. PCA9538A Product data sheet Low-voltage 8-bit I INPUT 2 I FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset. Block diagram of PCA9538A All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2012 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning RESET V Fig 2. 5.2 Pin description Table 3. Symbol A0 A1 RESET [1] P0 [1] P1 [ [1] P4 [1] P5 [1] P6 [1] P7 INT SCL SDA V DD [1] All I/O are configured as input at power-on. [2] HVQFN16 package die supply ground is connected to both the and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Fig 4. A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation ...
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... NXP Semiconductors 6.3 Interface definition Table 5. Byte 2 I C-bus slave address I/O data bus 6.4 Register descriptions 6.4.1 Input port register (00h) The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only ...
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... NXP Semiconductors 6.4.4 Configuration register (03h) The Configuration register (register 3) configures the direction of the I/O pins bit in this register is set to 1, the corresponding port pin is enabled as a high-impedance input bit in this register is cleared to 0, the corresponding port pin is enabled as an output. ...
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... NXP Semiconductors 6.6 Power-on reset When power (from applied reset condition until V released and the PCA9538A registers and I default states. After that, V operating voltage for a power-reset cycle. See 6.7 Reset input (RESET) The RESET input can be asserted to initialize the system while keeping the V operating level ...
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... NXP Semiconductors 7. Bus transactions The PCA9538A PCA9538A through write and read commands using I lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ...
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... NXP Semiconductors 7.2 Read commands To read data from the PCA9538A, the bus master must first send the PCA9538A address with the least significant bit set to a logic 0 (see command byte is sent after the address and determines which register accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1. ...
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... NXP Semiconductors 8. Application design-in information kΩ MASTER CONTROLLER SCL SDA INT RESET V SS Device address is 1110 000x for this example. P0, P2, P3 configured as outputs. P1, P4, P5 configured as inputs. P6, P7 are not used and need 100 k pull-up resistors to protect them from floating or the internal pull-up or pull-down selected ...
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... NXP Semiconductors 8.1 Minimizing I When the I/Os are used to control LEDs, they are normally connected to V resistor as shown in I about 1.2 V less than V I lower than V Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V Figure 12 than the LED supply voltage by at least 1 ...
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... NXP Semiconductors 8.3 Power-on reset requirements In the event of a glitch or data corruption, PCA9538A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application ...
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... NXP Semiconductors Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (t other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. how to measure these specifications. Fig 17. Glitch width and glitch height V is critical to the power-on reset ...
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... NXP Semiconductors 9. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I input/output clamping current IOK I LOW-level output current ...
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... NXP Semiconductors 12. Static characteristics Table 14. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter V input clamping voltage IK V power-on reset voltage POR I LOW-level output current OL V HIGH-level output voltage OH I input current I I HIGH-level input current ...
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... NXP Semiconductors Table 14. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter I supply current DD I additional quiescent DD supply current C input capacitance i C input/output capacitance io [1] For I , all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3 ...
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... NXP Semiconductors 12.1 Typical characteristics (μ 5 5 3.3 V 2 −40 −15 10 Fig 19. Supply current versus ambient temperature = 25 C T amb Fig 21. Supply current versus supply voltage PCA9538A Product data sheet Low-voltage 8-bit I 002aah333 I DD(stb) ( (°C) amb Fig 20 ...
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... NXP Semiconductors 35 I sink (mA −40 °C amb 25 ° ° 0 1. sink (mA −40 °C amb 25 ° ° 0 2 sink (mA −40 °C 60 amb 25 °C 85 ° 0 ...
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... NXP Semiconductors 30 I source (mA −40 °C amb 25 ° ° 0 1. source (mA −40 °C amb 25 ° ° 0 2 source T = −40 °C amb (mA) 25 °C 85 ° 0 5 Fig 23. I/O source current versus HIGH-level output voltage ...
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... NXP Semiconductors 120 V OL (mV) 100 ( (2) 40 (4) 20 (3) 0 −40 − sink ( sink ( 1 sink ( sink Fig 24. LOW-level output voltage versus temperature PCA9538A Product data sheet Low-voltage 8-bit I ...
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... NXP Semiconductors 13. Dynamic characteristics 2 Table 15. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 17. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 14. Parameter measurement information a. SDA load configuration ...
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... NXP Semiconductors a. Interrupt load configuration START condition slave address SDA SCL INT A t v(INT) A data into ADDRESS port INT t v(INT) Pn View Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices ...
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... NXP Semiconductors a. P port load configuration SCL SDA Pn b. Write mode (R SCL Pn c. Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors SDA DUT a. SDA load configuration START SCL SDA RESET t rec(rst RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9538A Product data sheet Low-voltage 8-bit I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of HVQFN16 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.50 4.00 4.00 2.20 2.20 12-03-07 Issue date 12-03-08 Fig 33. PCB footprint for SOT758-1 (HVQFN16); reflow soldering PCA9538A ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP16 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 34. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA9538A Product data sheet Low-voltage 8-bit (4x) P1 Generic footprint pattern ...
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... NXP Semiconductors 19. Abbreviations Table 20. Acronym ACPI CBT CDM CMOS DUT ESD FET FF GPIO HBM 2 I C-bus I/O LED LP LSB MSB PCB POR PRR SCR SMBus 20. Revision history Table 21. Revision history Document ID Release date PCA9538A v.1 20120928 PCA9538A Product data sheet Low-voltage 8-bit I Abbreviations ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... PCA9538A Product data sheet Low-voltage 8-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pointer register and command byte . . . . . . . . . 5 6.3 Interface definition . . . . . . . . . . . . . . . . . . . . . . 6 6.4 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 6.4.1 Input port register (00h ...