PCA9539AHF,128 NXP Semiconductors, PCA9539AHF,128 Datasheet
PCA9539AHF,128
Specifications of PCA9539AHF,128
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PCA9539AHF,128 Summary of contents
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PCA9539A Low-voltage 16-bit I Rev. 1 — 26 September 2012 1. General description The PCA9539A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander with interrupt and reset for I simple solution when additional I/Os are needed while keeping interconnections ...
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... NXP Semiconductors 2. Features and benefits C-bus to parallel port expander Pin and function compatible with PCA9539 Operating power supply voltage range of 1. 5.5 V Low standby current consumption: 1.5 A (typical 1.0 A (typical at 3 ...
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... NXP Semiconductors 4. Block diagram A0 A1 SCL SDA V DD RESET V SS Fig 1. PCA9539A Product data sheet Low voltage 16-bit I PCA9539A 2 I C-BUS/SMBus INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset. Block diagram of PCA9539A All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning RESET P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 V Fig 2. 5.2 Pin description Table 3. Symbol INT A1 RESET [2] P0_0 [2] P0_1 [2] P0_2 [2] P0_3 [2] P0_4 [2] P0_5 [2] P0_6 [2] P0_7 V SS [3] P1_0 [3] P1_1 [3] P1_2 [3] P1_3 [3] P1_4 [3] P1_5 PCA9539A Product data sheet Low voltage 16-bit I ...
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... NXP Semiconductors Table 3. Symbol [3] P1_6 [3] P1_7 A0 SCL SDA V DD [1] HWQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 6.2 Registers 6.2.1 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCA9539A. The lower four bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected ...
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... NXP Semiconductors 6.2.3 Output port register pair (02h, 03h) The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that was written to these registers, not the actual pin value ...
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... NXP Semiconductors Table 12. Bit Symbol Default 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V If the I/O is configured as an output enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either V recommended levels for proper operation ...
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... NXP Semiconductors 6.5 RESET input The RESET input can be asserted to initialize the system while keeping the V operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of t changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the ports can be changed externally or through the master. This input requires a pull-up resistor ...
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SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 7. Write ...
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... NXP Semiconductors 7.2 Reading the port registers In order to read data from the PCA9539A, the bus master must first send the PCA9539A address with the least significant bit set to a logic 0 (see address”). The command byte is sent after the address and determines which register will be accessed ...
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INT INT t t v(INT) rst(INT) SCL R/W slave address I0.x SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT) rst(INT) SCL R/W slave address I0.x SDA ...
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... NXP Semiconductors 8. Application design-in information kΩ MASTER CONTROLLER SCL SDA INT RESET V SS Device address configured as 1110 100X for this example. P0_0, P0_2, P0_3 configured as outputs. P0_1, P0_4, P0_5 configured as inputs. P0_6, P0_7 and P1_0 to P1_7 configured as inputs. ...
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... NXP Semiconductors Fig 13. High value resistor in parallel with 8.2 Power-on reset requirements In the event of a glitch or data corruption, PCA9539A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application ...
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... NXP Semiconductors Table 13. Recommended supply sequencing and ramp rates (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter (dV/dt) fall rate of change of voltage f (dV/dt) rise rate of change of voltage r t reset delay time d(rst) V glitch supply voltage difference DD(gl) t supply voltage glitch pulse width ...
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... NXP Semiconductors 9. Limiting values Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output clamping current OK I input/output clamping current IOK I LOW-level output current ...
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... NXP Semiconductors 12. Static characteristics Table 17. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter V input clamping voltage IK V power-on reset voltage POR I LOW-level output current OL V HIGH-level output voltage OH V LOW-level output voltage OL I input current ...
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... NXP Semiconductors Table 17. Static characteristics + 1. 5.5 V; unless otherwise specified. amb DD Symbol Parameter I supply current DD I additional quiescent DD supply current C input capacitance i C input/output capacitance io R internal pull-up resistance pu(int) [1] For I , all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3 ...
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... NXP Semiconductors 12.1 Typical characteristics (μ 5 5 3.3 V 2 −40 −15 10 Fig 19. Supply current versus ambient temperature = 25 C T amb Fig 21. Supply current versus supply voltage PCA9539A Product data sheet Low voltage 16-bit I 002aah333 I DD(stb) ( (° ...
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... NXP Semiconductors 35 I sink (mA −40 °C amb 25 ° ° 0 1. sink (mA −40 °C amb 25 ° ° 0 2 sink (mA −40 °C 60 amb 25 °C 85 ° 0 ...
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... NXP Semiconductors 30 I source (mA −40 °C amb 25 ° ° 0 1. source (mA −40 °C amb 25 ° ° 0 2 source T = −40 °C amb (mA) 25 °C 85 ° 0 5 Fig 23. I/O source current versus HIGH-level output voltage ...
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... NXP Semiconductors 120 V OL (mV) 100 ( (2) 40 (4) 20 (3) 0 −40 − sink ( sink ( 1 sink ( sink Fig 24. LOW-level output voltage versus temperature PCA9539A Product data sheet Low voltage 16-bit I ...
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... NXP Semiconductors 13. Dynamic characteristics 2 Table 18. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 20. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 14. Parameter measurement information a. SDA load configuration ...
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... NXP Semiconductors a. Interrupt load configuration START condition slave address SDA SCL INT A t v(INT) A data into ADDRESS port INT t v(INT) Pn View Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices ...
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... NXP Semiconductors a. P port load configuration SCL SDA Pn b. Write mode (R SCL Pn c. Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors SDA DUT a. SDA load configuration START SCL SDA RESET t rec(rst RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors 15. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9539A Product data sheet Low voltage 16-bit I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP24 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 33. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCA9539A Product data sheet Low voltage 16-bit I ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN24 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.500 5.000 5.000 3.200 3.200 07-09-24 Issue date 09-06-15 Fig 34. PCB footprint for SOT994-1 (HWQFN24); reflow soldering ...
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... NXP Semiconductors 19. Abbreviations Table 23. Acronym ACPI CBT CDM CMOS ESD FET FF GPIO HBM 2 I C-bus I/O LED PCB POR SMBus 20. Revision history Table 24. Revision history Document ID Release date PCA9539A v.1 20120926 PCA9539A Product data sheet Low voltage 16-bit I Abbreviations Description Advanced Configuration and Power Interface ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... PCA9539A Product data sheet Low voltage 16-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 Pointer register and command byte . . . . . . . . . 6 6.2.2 Input port register pair (00h, 01h 6.2.3 Output port register pair (02h, 03h ...