PCAL9535AHF,128 NXP Semiconductors, PCAL9535AHF,128 Datasheet - Page 9

• Manufacturer Part Number: PCAL9535AHF,128
• Description: Interface - I/O Expanders 16bit I2C IO Port Interrupt and Agile
• Manufacturer: NXP Semiconductors

Specifications of PCAL9535AHF,128

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HWQFN-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCAL9535A
Product data sheet
6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h)
6.2.7 Input latch register pair (44h, 45h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO
can be configured independently to a certain output current level by two register control
bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is
controlled by register 41 CC0.6(bits [5:4]). The output drive level of the GPIO is
programmed 00b = 0.25, 01b = 0.50, 10b = 0.75, or 11b = 1 of the maximum drive
capability of the I/O. See
described in
Table 13.
Table 14.
Table 15.
Table 16.
The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O
pins. These registers are effective only when the pin is configured as an input port. When
an input latch register bit is 0, the corresponding input pin state is not latched. A state
change of the corresponding input pin generates an interrupt. A read of the input register
clears the interrupt. If the input goes back to its initial logic state before the input port
register is read, then the interrupt is cleared.
When an input latch register bit is 1, the corresponding input pin state is latched. A change
of state in the input generates an interrupt and the input logic value is loaded into the
corresponding bit of the input port register (registers 0 and 1). A read of the input port
register clears the interrupt. If the input pin returns to its initial logic state before the input
port register is read, then the interrupt is not cleared and the corresponding bit of the input
port register keeps the logic value that initiated the interrupt. See
port register (latch enabled), scenario
For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to
logic 0, the input port 0 register will capture this change and an interrupt is generated (if
unmasked). When the read is performed on the input port 0 register, the interrupt is
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Current control port 0 register (address 40h)
Current control port 0 register (address 41h)
Current control port 1 register (address 42h)
Current control port 1 register (address 43h)
Section 7.1
7
1
7
1
7
1
7
1
All information provided in this document is subject to legal disclaimers.
CC0.3
CC0.7
CC1.3
CC1.7
Rev. 1 — 28 September 2012
Low-voltage 16-bit I
6
1
6
1
6
1
6
1
Section 8.2 “Output drive strength
and a register pair read is described in
5
1
5
1
5
1
5
1
CC0.2
CC0.6
CC1.2
CC1.6
3”.
2
4
1
4
1
4
1
4
1
C-bus I/O port with interrupt and Agile I/O
3
1
3
1
3
1
3
1
CC0.1
CC0.5
CC1.1
CC1.5
control”. A register pair write is
PCAL9535A
2
1
2
1
2
1
2
1
Section
Figure 12 “Read input
© NXP B.V. 2012. All rights reserved.
7.2.
1
1
1
1
1
1
1
1
CC0.0
CC0.4
CC1.0
CC1.4
0
1
0
1
0
1
0
1
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