PCA9539APW,118 NXP Semiconductors, PCA9539APW,118 Datasheet - Page 11

• Manufacturer Part Number: PCA9539APW,118
• Description: Interface - I/O Expanders 16bit I2C IO Port
• Manufacturer: NXP Semiconductors

Specifications of PCA9539APW,118

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCA9539A
Product data sheet
Fig 9.
SDA
(cont.)
Remark: Transfer can be stopped at any time by a STOP condition.
Read from register
S
START condition
S
(repeated)
START condition
1
7.2 Reading the port registers
1
1
slave address
1
1
slave address
1
In order to read data from the PCA9539A, the bus master must first send the PCA9539A
address with the least significant bit set to a logic 0 (see
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte is
sent by the PCA9539A (see
register on the falling edge of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data now reflects the information in the other register
in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is
no limit on the number of data bytes received in one read transmission, but on the final
byte received the bus master must not acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
0
0
1 A1 A0
1 A1 A0 1
acknowledge
acknowledge
from slave
R/W
from slave
0
R/W
A
All information provided in this document is subject to legal disclaimers.
A
0
MSB
0/1 0
Rev. 1 — 26 September 2012
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
upper byte of register
command byte
data from lower or
DATA (first byte)
Low voltage 16-bit I
0 0/1 0/1 0/1 0/1
Figure
acknowledge
from slave
9,
Figure 10
LSB
A
A
acknowledge
from master
(cont.)
2
and
C-bus I/O port with interrupt and reset
MSB
Figure
lower byte of register
data from upper or
DATA (last byte)
Figure 4 “PCA9539A device
11). Data is clocked into the
no acknowledge
from master
PCA9539A
LSB
© NXP B.V. 2012. All rights reserved.
NA
002aah064
P
STOP
condition
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