PCA6408AHKX NXP Semiconductors, PCA6408AHKX Datasheet - Page 15

• Manufacturer Part Number: PCA6408AHKX
• Description: Interface - I/O Expanders 8bit IO Expander Low Voltage XQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA6408AHKX

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: XQFN-16
• Operating Current: 200 mA
• Output Current: 10 mA
• Product Type: I/O Expanders

NXP Semiconductors
Table 11.
T
[1]
[2]
PCA6408A
Product data sheet
Symbol
(dV/dt)
(dV/dt)
t
V
t
V
d(rst)
w(gl)VDD
amb
POR(trip)
DD(gl)
Level that V
Glitch width that will not cause a functional disruption when V
= 25
f
r

C (unless otherwise noted). Not tested; specified by design.
Recommended supply sequencing and ramp rates
Parameter
fall rate of change of voltage
rise rate of change of voltage
reset delay time
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
DD(P)
can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when t
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance.
how to measure these specifications.
V
is released and all the registers and the I
their default states. The value of V
0 V.
Fig 17. Glitch width and glitch height
Fig 18. Power-on reset voltage (V
POR
V
V
POR
POR
Figure 18
is critical to the power-on reset. V
(falling V
(rising V
V
DD(P)
DD(P)
DD(P)
∆V
and
All information provided in this document is subject to legal disclaimers.
DD(gl)
V
)
)
POR
DD(P)
Table 11
Rev. 1 — 27 September 2012
Condition
Figure 15
Figure 15
Figure
V
Figure
V
Figure 17
Figure 17
falling V
rising V
DD(P)
DD(P)
w(gl)VDD
provide more details on this specification.
drops to V
drops to V
15; re-ramp time when
16; re-ramp time when
DD(P)
DD(P)
DD(gl)
t
w(gl)VDD
) and glitch height (V
POR
Low-voltage, 8-bit I
POR
= 0.5  V
Figure 17
SS
POR(min)
)
differs based on the V
POR
2
C-bus/SMBus state machine are initialized to
is the voltage level at which the reset condition
DD(P)
 50 mV
and
.
Table 11
2
DD(gl)
C-bus and SMBus I/O expander
[1]
[2]
Min
0.1
0.1
1
1
-
-
0.7
-
provide more information on
DD(P)
) are dependent on each
being lowered to or from
PCA6408A
Typ
-
-
-
-
-
-
-
-
w(gl)VDD
© NXP B.V. 2012. All rights reserved.
< 1 s.
Max
2000
2000
-
-
1.0
10
-
1.4
002aag962
time
002aag963
15 of 40
Unit
ms
ms
s
s
V
s
V
V
time
time