MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 13

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MAX9240GTM+

Manufacturer Part Number
MAX9240GTM+
Description
Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX9240GTM+

Rohs
yes
Maxim Integrated
PIN
1
2
3
4
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
GPIO1/BWS
GPIO0/DBL
I2CSEL
NAME
CX/TP
Coax or STP Cable With Line Fault Detect
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
GPIO/Double-Mode Input. Function is determined by the state of LCCEN (Table 13).
Coax/Twisted-Pair Three-Level Configuration Input (Table 8)
I
Set I2CSEL = high to select I
2
C Select. Control-channel interface protocol select input with internal pulldown to EP.
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input latch. Set
BWS = high for 30-bit input latch.
GPIO0 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI pullup to IOVDD.
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use double-input mode.
Set DBL = low to use single-input mode.
MS/ HVEN
PCLKOUT
TOP VIEW
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
IOVDD
AVDD
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
1
CONNECT EP TO GROUND PLANE
+
2
3
(7mm x 7mm X 0.75mm)
EP
4
2
C slave interface. Set I2CSEL = low to select UART interface.
5
MAX9240
TQFN
6
7
8
9
FUNCTION
10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
DOUT20
DOUT21/HS0
DOUT22/VS0
DOUT23/HS1
IOVDD
DOUT24/VS1
LFLT
LMN1
LMN0
LOCK
ERR
PWDN
Pin Configuration
Pin Description
MAX9240
13

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