MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 14

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

Maxim Integrated
6, 48
PIN
10
11
12
13
14
15
5
7
8
9
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
RX/SDA/EDC
TX/SCL/ES
LCCEN
NAME
PWDN
AVDD
DVDD
LOCK
ERR
IN+
GPI
IN-
Coax or STP Cable With Line Fault Detect
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables the control-
channel interface pins. LCCEN = low disables the control-channel interface pins and selects an
alternate function on the indicated pins (Table 13).
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
Noninverting Coax/Twisted-Pair Serial Input
Inverting Coax/Twisted-Pair Serial Input
General-Purpose Input. The GMSL deserializer GPI (or INT) input follows GPI.
Receive/Serial Data/Error Detection Correction. Function is determined by the state of LCCEN (Table 13).
Transmit/Serial Clock/Edge Select. Function is determined by the state of LCCEN (Table 13).
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
Active-Low Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode
to reduce power consumption.
Error Output. Open-drain data error detection and/or correction indication output with internal 60kI
pullup to IOVDD. ERR is an open-drain driver and requires a pullup resistor.
Open-Drain Lock Output with Internal 60kI Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active
or during PRBS test. LOCK is high impedance when PWDN = low. LOCK is an open-drain driver and
requires a pullup resistor.
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA
is the Rx input of the MAX9240’s UART. In the I
MAX9240’s I
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable error detection
correction. Set EDC = low to disable error detection correction.
TX/SCL (LCCEN = high). Input/output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL
is the Tx output of the MAX9240’s UART. In the I
MAX9240’s I
ES (LCCEN = low): Input with internal pulldown to EP. When ES is high, PCLKOUT indicates valid
data on the falling edge of PCLKOUT. When ES is low, PCLKOUT indicates valid data on the rising
edge of PCLKOUT. Do not change the ES input while the pixel clock is running.
2
2
C master/slave. RX/SDA has an open-drain driver and requires a pullup resistor.
C master/slave. TX/SCL has an open-drain driver and requires a pullup resistor.
FUNCTION
2
C mode, RX/SDA is the SDA input/output of the
2
C mode, TX/SCL is the SCL input/output of the
Pin Description (continued)
MAX9240
14