MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 27

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

The serializer uses differential CML signaling to drive
twisted-pair cable and single-ended CML to drive
coax cable with programmable pre/deemphasis and
AC-coupling. The deserializer uses AC-coupling and
programmable channel equalization.
Input data is scrambled and then 8b/10b coded. The
deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error-correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is
the parity bit of the previous 23 or 31 bits
The serializer uses the reverse control channel to receive
I
Table 3. Data-Rate Selection Table
Figure 15. Serial-Data Format
Maxim Integrated
2
C/UART and GPO signals from the deserializer in the
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
D0
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Serial Link Signaling and Data Format
DRS SETTING
D1
CORRECTION DATA
VIDEO AND ERROR
0
0
0
0
1
1
1
1
Coax or STP Cable With Line Fault Detect
24 BITS
Reverse Control Channel
D21
CHANNEL BIT
CONTROL-
FORWARD
FCC
1 (double input)
DBL SETTING
0 (single input)
CHECK BIT
(Figure
PACKET
PARITY
PCB
0
1
0
0
1
1
15).
D0
opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable, forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after start-
ing/stopping the forward serial link.
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKOUT frequency range
for a PCLKOUT frequency range of 6.25MHz to 12.5MHz
(32-bit, single-output mode) or 8.33MHz to 16.66MHz
(24-bit, single-output mode). Set DRS = 0 for normal
operation. It is not recommended to use double-output
mode when DRS = 1.
D1
BWS SETTING
0 (24-bit mode)
1 (32-bit mode)
0
1
0
1
0
1
CORRECTION DATA
VIDEO AND ERROR
32 BITS
PCLKOUT RANGE (MHz)
Data-Rate Selection
(Table
MAX9240
8.33 to 16.66
6.25 to 12.5
Do Not Use
Do Not Use
16.66 to 50
33.3 to 100
D29
12.5 to 35
25 to 75
3). Set DRS = 1
CHANNEL BIT
CONTROL-
FORWARD
FCC
CHECK BIT
PACKET
PARITY
PCB
27