MAX9240GTM+ Maxim Integrated, MAX9240GTM+ Datasheet - Page 46

• Manufacturer Part Number: MAX9240GTM+
• Description: Serializers & Deserializers - Serdes 28Bit GMSL Deserializer
• Manufacturer: Maxim Integrated

Specifications of MAX9240GTM+

• Rohs: yes

Table 16. Register Table (see
Maxim Integrated
REGISTER
ADDRESS
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
0x06
0x07
D[7:0]
D[1:0]
BITS
D7
D6
D5
D4
D3
D2
Coax or STP Cable With Line Fault Detect
HVTRACK
NAME
HVEN
BWS
EDC
DBL
DRS
ES
—
00000010
VALUE
Table
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
1) (continued)
Reserved.
Single-input mode. Power-up default when LCCEN =
high or GPIO0/DBL = low.
Double-input mode. Power-up default when LCCEN =
low and GPIO0/DBL = high.
High data-rate mode.
Low data-rate mode.
24-bit mode. Power-up default when LCCEN = high or
GPIO1/BWS = low.
32-bit mode. Power-up default when LCCEN = low and
GPIO1/BWS = high.
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = high or TX/SCL/ES
= low. Do not change this value while the pixel clock is
running.
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = low and TX/SCL/ES
= high. Do not change this value while the pixel clock is
running.
HS/VS tracking disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
HS/VS tracking enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
HS/VS encoding disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
HS/VS encoding enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
1-bit parity error detection (GMSL compatible).
Power-up default when LCCEN = high or RX/SDA/
EDC = low.
6-bit CRC error detection.
6-bit hamming code (single-bit error correct, double-
bit error detect) and 16-word interleaving. Power-up
default when LCCEN = low and RX/SDA/EDC = high.
Do not use.
FUNCTION
MAX9240
DEFAULT
00000010
VALUE
00, 10
0, 1
0, 1
0, 1
0, 1
0, 1
0
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