C8051F552-IMR Silicon Labs, C8051F552-IMR Datasheet - Page 100

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C8051F552-IMR

Manufacturer Part Number
C8051F552-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F552-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F55x/56x/57x
On exit from the PCA interrupt service routine, the CIP-51 will return to the CAN0 ISR. On execution of the
RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the
SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Soft-
ware in the CAN0 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise, the con-
tents of SFRLAST are moved to the SFRNEXT register. Recall this was the SFR Page value 0x00 being
used to access SPI0DAT before the CAN0 interrupt occurred. See Figure 12.5.
100
SFRPAGE
SFRNEXT
SFRNEXT
SFRLAST
popped to
popped to
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt
(SPI0DAT)
stack on return from
popped off of the
(CAN0)
SFR Page 0x0
Automatically
0xC
0x0
interrupt
Rev. 1.1
SFRPAGE
SFRNEXT
SFRLAST

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