C8051F552-IMR Silicon Labs, C8051F552-IMR Datasheet - Page 99

• Manufacturer Part Number: C8051F552-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F552-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the CAN0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x0C for CAN0) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x00 for SPI0DAT) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be
overwritten. See Figure 12.4.
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR
SFRPAGE
SFRNEXT
SFRNEXT
pushed to
SFRLAST
pushed to
(SPI0DAT)
SFRPAGE on PCA
pushed on stack in
(CAN0)
SFR Page 0x0
Automatically
(PCA)
0xC
0x0
0x0
interrupt
Rev. 1.1
C8051F55x/56x/57x
SFRPAGE
SFRNEXT
SFRLAST
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