C8051F552-IMR Silicon Labs, C8051F552-IMR Datasheet - Page 184

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C8051F552-IMR

Manufacturer Part Number
C8051F552-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 32 kB 2 kB LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F552-IMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
C8051F55x/56x/57x
SFR Definition 19.17. P1MDIN: Port 1 Input Mode
SFR Address = 0xF2; SFR Page = 0x0F
SFR Definition 19.18. P1MDOUT: Port 1 Output Mode
SFR Address = 0xA5; SFR Page = 0x0F
184
Name
Reset
Name
Reset
7:0
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
Bit
Bit
Type
Type
Bit
Bit
P1MDIN[7:0]
Name
Name
7
1
7
0
Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P1MDOUT register.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
These bits are ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
6
1
6
0
5
1
5
0
Rev. 1.1
P1MDOUT[7:0]
4
1
4
0
P1MDIN[7:0]
R/W
R/W
Function
Function
3
1
3
0
2
1
2
0
1
1
1
0
0
1
0
0

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