73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 32

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73S1217F-68MR/F/PE

Manufacturer Part Number
73S1217F-68MR/F/PE
Description
8-bit Microcontrollers - MCU
Manufacturer
Maxim Integrated
Datasheet

Specifications of 73S1217F-68MR/F/PE

Rohs
yes
Core
80515
Data Bus Width
8 bit
Part # Aliases
90-W1217+TF5
Miscellaneous Control Register 1 (MISCtl1): 0xFFF2
*Note: The ANAPEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
32
MISCtl1.7
MISCtl1.6
MISCtl1.5
MISCtl1.4
MISCtl1.3
MISCtl1.2
MISCtl1.1
MISCtl1.0
Bit
MSB
ANAPEN*
USBCON
USBPEN
Symbol
FLSH66
FRPEN
Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is
passed through with no change. When FRPEN = 0 a one-shot circuit that
shortens the Flash Read signal is enabled to save power. The Flash Read
pulse will shorten to 40 or 66ns (approximate based on the setting of the
FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock
frequencies greater than 10MHz, this bit should be set high.
When high, creates a 66ns Flash read pulse, otherwise creates a 40ns read
pulse when FRPEN is set.
0 = Enable the analog functions that generate VREF and bias current
functions. Setting high will turn off the VPD regulator and VCO/PLL
functions.
0 = Enable the USB differential transceiver.
USB pull-up resistor connect enable.
FRPEN
Table 16: The MISCtl1 Register
FLSH66
0x10
Function
ANAPEN USBPEN USBCON
LSB
Rev. 1.2

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