73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 67

• Manufacturer Part Number: 73S1217F-68MR/F/PE
• Description: 8-bit Microcontrollers - MCU
• Manufacturer: Maxim Integrated

Specifications of 73S1217F-68MR/F/PE

• Rohs: yes
• Core: 80515
• Data Bus Width: 8 bit
• Part # Aliases: 90-W1217+TF5

(column/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce
timer. Debouncing time is adjustable through the
1.7.14 Keypad Interface
The 73S1217F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches)
interface using 11 dedicated I/O pins. Figure 13 shows a simplified block diagram of the keypad
interface.
There are five drive lines (outputs) corresponding to columns and six sense lines (inputs) corresponding
to rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external
resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for
a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense
Rev. 1.2
KCOL Register
7
73S1217F
6
5
4
KROW Register
3
7
Column Value
Keypad Clock
2
6
(1)
1
5
Hardware Scan Enable
0
4
Row Value
3
5
2
Keypad Clock
KSTAT Register
1
7
Figure 13: Simplified Keypad Block Diagram
0
6
5
Scan
6
4
KORDERL / H Registers
7
7
KSIZE Register
3
6
6
2
5
Debouncing
Dividers
7
5
1
4
4
6
0
3
3
5
0
2
2
4
KSCAN
1
1
6
VDD
KSCAN Register
3
1
2
0
2
0
3
1
4
1kHz
register. Internal hardware circuitry performs
0
5
6
VDD
(2)
7
COL4:0
(1) KCOL is normally used as Read only
register. When hardware keyscan mode
is disabled, this register is to be used by
firmware to write the column data to
handle firmware scanning.
(2) 1kHz internal clock signal can be
selected either from the PLL (= from the
12MHz main clock), or from the 32kHz
system clock.
If smaller keypad than 6x 5 is to be
implemented, unused row inputs
should be connected to VDD. Unused
column outputs should be left
unconnected.
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