73S1217F-68MR/F/PE Maxim Integrated, 73S1217F-68MR/F/PE Datasheet - Page 35
![no-image](/images/no-image-200.jpg)
73S1217F-68MR/F/PE
Manufacturer Part Number
73S1217F-68MR/F/PE
Description
8-bit Microcontrollers - MCU
Manufacturer
Maxim Integrated
Datasheet
1.73S1217F-68MRFPE.pdf
(140 pages)
Specifications of 73S1217F-68MR/F/PE
Rohs
yes
Core
80515
Data Bus Width
8 bit
Part # Aliases
90-W1217+TF5
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corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
1.7.5
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other
parts of the 73S1217F, for example the USB interface, USR I/O, RTC, smart card interface, analog
comparators, etc. The external interrupt configuration is shown in Figure 9.
.
Rev. 1.2
Interrupts
Card_Det
VCC_OK
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
KeyPad
Serial
Serial
Analog
Ch 0
Ch 1
INT3
INT2
Comp
USB
RTC
I
2
VccCTL
C
CRDCtl
Figure 9: External Interrupt Configuration
Pads
Pads
USR
INT
+
VDD_Fault
Card Event
VCC_TMR
USR
Ctl
USR
Int
Ctl
Wait Tim eout
USR
Int
Int
Ctl
USR
Int
Ctl
TX_Event
RX_Error
TX_Error
Tx_Sent
RxData
INT5
INT6
Ctl
Ctl
PDMUXCtl
SCInt
when PWRDN bit is s et
+
During STOP, IDLE
SCIE
Delay
0
1
+
int4
int5
int6
SerChan 0 int
SerChan 1 int
t0
int0
t1
int1
int2
int3
Clear PWRDN bit
CORE
MPU
35
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