C8051F996-GUR Silicon Labs, C8051F996-GUR Datasheet - Page 118

• Manufacturer Part Number: C8051F996-GUR
• Description: 8-bit Microcontrollers - MCU 8kB ADC 14-CH CDC
• Manufacturer: Silicon Labs

Specifications of C8051F996-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F99x-C8051F98x
9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop
software. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the
analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
9.1.
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the
standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24
system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the
CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking
more than eight system clock cycles.
118
- Fully Compatible with MCS-51 Instruction
- 25 MIPS Peak Throughput with 25 MHz
- 0 to 25 MHz Clock Frequency
CIP-51 Microcontroller
Set
Clock
Performance
RESET
CLOCK
STOP
IDLE
Figure 9.1. CIP-51 Block Diagram
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
Rev. 1.1
TMP2
DATA BUS
DATA BUS
D8
D8
D8
A16
D8
D8
D8
D8
B REGISTER
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
REGISTER
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
ADDRESS
MEMORY
SRAM
SFR
BUS
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
SFR_READ_DATA
SRAM
MEM_ADDRESS
MEM_CONTROL
EMULATION_IRQ
SFR_ADDRESS
SFR_CONTROL
SYSTEM_IRQs