74LVT16500ADL,518 NXP Semiconductors, 74LVT16500ADL,518 Datasheet

IC UNIV BUS TXRX 18BIT 56SSOP

74LVT16500ADL,518

Manufacturer Part Number
74LVT16500ADL,518
Description
IC UNIV BUS TXRX 18BIT 56SSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT16500ADL,518

Logic Type
Universal Bus Transceiver
Number Of Circuits
18-Bit
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVT16500ADL-T
74LVT16500ADL-T
935194780518
1. General description
2. Features
The 74LVT16500A is a high-performance BiCMOS product designed for V
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
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74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 — 29 May 2006
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Negative edge-triggered clock inputs
Latch-up protection:
ESD protection:
N
N
N
JESD78: exceeds 500 mA
MIL STD 883 Method 3015: exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
Product data sheet
CC
operation at

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74LVT16500ADL,518 Summary of contents

Page 1

V 18-bit universal bus transceiver; 3-state Rev. 03 — 29 May 2006 1. General description The 74LVT16500A is a high-performance BiCMOS product designed for V 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus ...

Page 2

Philips Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVT16500ADGG +85 C 74LVT16500ADL + Functional diagram ...

Page 3

Philips Semiconductors Fig 3. Logic diagram 74LVT16500A_3 Product data sheet 3.3 V 18-bit universal bus transceiver; 3-state 1 OEAB 55 CPAB 2 LEAB 28 LEBA 30 CPBA 27 OEBA CLK to 17 other channels Rev. 03 ...

Page 4

Philips Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol OEAB LEAB A0 GND 74LVT16500A_3 Product data sheet 3.3 V 18-bit universal bus transceiver; 3-state 74LVT16500A 1 OEAB 2 ...

Page 5

Philips Semiconductors Table 2. Symbol GND A10 A11 GND A12 A13 A14 V CC A15 A16 GND A17 OEBA LEBA GND CPBA B17 GND B16 B15 V CC B14 B13 B12 GND B11 ...

Page 6

Philips Semiconductors Table 2. Symbol GND B0 CPAB GND 6. Functional description Table 3. Operating mode disabled disabled, latch data disabled, latch data disabled, hold data disabled, clock data disabled, clock data transparent transparent latch ...

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Philips Semiconductors 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter ...

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Philips Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter [ amb V input clamping voltage IK V HIGH-level ...

Page 9

Philips Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional quiescent supply CC current C input capacitance i C input/output capacitance io [1] Typical values are at ...

Page 10

Philips Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t setup time LOW su( CPAB CPBA An to LEAB with CPAB LOW or ...

Page 11

Philips Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t hold time HIGH h( CPAB CPBA An to LEAB LEBA ...

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Philips Semiconductors Fig 6. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA) Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable Fig 8. 3-state output enable time to HIGH-level and ...

Page 13

Philips Semiconductors Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level Fig 10. Data setup and hold times Table 8. Supply voltage 2.7 V 3.3 V 74LVT16500A_3 Product data sheet OEBA V I input 0 ...

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Philips Semiconductors Fig 11. Load circuitry for switching times Table 9. Input V I 2.7 V 74LVT16500A_3 Product data sheet negative V M pulse ...

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Philips Semiconductors 12. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. ...

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Philips Semiconductors SSOP56: plastic shrink small outline package; 56 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm ...

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Philips Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVT16500A_3 20060529 • Modifications: ...

Page 18

Philips Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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Philips Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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