74ALVC162334ADGG,5 NXP Semiconductors, 74ALVC162334ADGG,5 Datasheet - Page 11

• Manufacturer Part Number: 74ALVC162334ADGG,5
• Description: IC UNIV BUS DVR 16BIT 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCr

Specifications of 74ALVC162334ADGG,5

• Logic Type: Universal Bus Driver
• Number Of Circuits: 16-Bit
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 2.3 V ~ 2.7 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVC162334ADG; 74ALVC162334ADG; 935267301512

NXP Semiconductors
74ALVC162334A_3
Product data sheet
Fig 5. Input (An) to output (Yn) propagation delay
Fig 7. Data set-up and hold times, An input to
Fig 9. Data set-up and hold times, An input to
Yn output
input
input
An input
An
LE
output
input
input
CP
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
LE input
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
CP input
An
Yn
V
M
11.1 AC waveforms
t
su
V
V
M
t
M
PHL
t
V
su
M
V
V
t
h
t
V
h
CC
CC
M
V
V
V
V
M
OL
M
OL
= 3.0 V to 3.6 V and V
= 2.3 V to 2.7 V and V
= 1.5 V; V
= 0.5 V; V
and V
and V
V
M
t
OH
OH
t
su
t
PLH
su
X
are the typical output voltage drop that occur with the output load.
X
are the typical output voltage drop that occur with the output load.
t
h
t
= V
= V
h
V
002aac730
M
Rev. 03 — 13 December 2006
002aac728
002aac726
OL
OL
V
GND
V
GND
V
V
I
I
OH
OL
V
GND
V
GND
+ 0.3 V; V
+ 0.15 V; V
V
GND
V
V
I
I
I
OH
OL
CC
CC
= 2.7 V range:
< 2.3 V range:
Fig 6. LE input pulse width, LE input to Yn output
Fig 8. CP to Yn propagation delays, clock pulse width,
Fig 10. 3-state enable and disable times
Y
HIGH-to-OFF
OFF-to-HIGH
OFF-to-LOW
LOW-to-OFF
Y
= V
= V
OE input
Yn output
Yn output
CP input
LE input
OH
output
output
OH
propagation delays
and maximum clock frequency
0.3 V; V
0.15 V; V
V
enabled
outputs
M
I
V
V
74ALVC162334A
t
= 2.7 V.
M
M
PLZ
16-bit registered driver (3-state)
t
PHZ
t
t
I
w
w
= V
1 / f
t
t
PHL
PHL
V
V
max
CC
M
M
V
.
X
V
Y
disabled
outputs
t
t
PLH
PLH
V
V
M
M
© NXP B.V. 2006. All rights reserved.
t
PZL
t
PZH
002aac727
002aac729
V
M
V
enabled
M
outputs
V
GND
V
V
V
GND
V
V
002aac731
I
OH
OL
I
OH
OL
11 of 19
V
GND
V
V
V
GND
I
CC
OL
OH