74ALVCH162601DGG,1 NXP Semiconductors, 74ALVCH162601DGG,1 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH162601DGG,1
• Description: IC UNIV BUS TXRX 18BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH162601DGG,1

• Logic Type: Universal Bus Transceiver
• Number Of Circuits: 18-Bit
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH162601DG; 74ALVCH162601DG; 935262800112

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
Ground = 0; T
Notes
1. C
2. The condition is V
1999 Oct 14
t
C
C
C
PHL
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
standard pin-out architecture
Low inductance multiple V
ground pins for minimum noise and
ground bounce
All data inputs have bus hold
circuitry
Integrated 30
resistors.
I/O
I
PD
18-bit universal bus transceiver with 30
termination resistor; 3-state
P
f
f
C
V
i
o
/t
D
CC
SYMBOL
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
(C
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
L
PD
V
CC
amb
V
2
CC
flow-through
= 25 C; t
termination
f
2
o
) = sum of outputs;
propagation delay A
input/output capacitance
input capacitance
power dissipation capacitance per
latch
I
f
= GND to V
i
+
r
CC
= t
(C
f
L
and
PARAMETER
= 2.5 ns.
CC
V
CC
.
2
DESCRIPTION
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OE
latched if CP
(CP
transparent mode when LE
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CP
When OE
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CE
Data flow for B-to-A is similar to that of A-to-B but uses OE
To ensure the high-impedance state during power-down, OE
should be tied to V
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
n
f
, B
o
) where:
AB
n
to B
and CP
AB
n
, A
AB
is LOW, the outputs are active. When OE
n
BA
is held at a HIGH or LOW logic level. If LE
) inputs. For A-to-B data flow, the device operates in the
C
C
notes 1 and 2
2
CC
L
L
outputs enabled
outputs disabled
= 30 pF; V
= 50 pF; V
through a pull-up resistor, the minimum value of the
D
BA
in W).
CONDITIONS
/CE
AB
AB
is HIGH. When LE
CC
CC
).
= 2.5 V
= 3.3 V
series resistors in both HIGH or
AB
4.0
3.1
8.0
4.0
21
3
74ALVCH162601
TYPICAL
AB
is LOW, the A data is
and OE
AB
Product specification
AB
is HIGH, the outputs
BA
is LOW, the A-bus
BA
, LE
BA
and OE
), and clock
ns
ns
pF
pF
pF
pF
BA
and CP
UNIT
AB
AB
.
BA
.