IDT74ALVCH16901PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16901PAG Datasheet - Page 3

• Manufacturer Part Number: IDT74ALVCH16901PAG
• Description: IC UNIV BUS TXRX 18BIT 64TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74ALVCHr

Specifications of IDT74ALVCH16901PAG

• Logic Type: Universal Bus Transceiver, CMOS
• Number Of Circuits: 18-Bit
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16901PAG

FUNCTION TABLE
NOTES:
1. H = HIGH Voltage Level
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
3. Output level before the indicated steady-state conditions were established.
4. Output level before the indicated steady-state conditions were established,
PARITY
NOTES:
1. Parity output is set to the level so that the specific bus side is set to even parity.
2. Parity output is set to the level so that the specific bus side is set to odd parity.
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
CLKENAB
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
and CLKENBA.
provided that CLKAB was LOW before LEAB went LOW.
SEL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
L
L
L
L
OEBA
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
OEAB
H
L
L
L
L
L
L
L
OEAB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
Inputs
LEAB
H
H
X
L
L
L
L
L
ODD/EVEN
(1,2)
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
CLKAB
↑
↑
H
X
X
X
X
L
∑ ∑ ∑ ∑ ∑ OF INPUTS
A1-− − − − − A8 = H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
Inputs
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
xAx
H
H
X
X
X
X
L
L
Outputs
xBx
B
B
B
∑ ∑ ∑ ∑ ∑ OF INPUTS
H
H
B1—− − − − − B8 = H
Z
L
L
(3)
(3)
(4)
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
0, 2, 4, 6, 8
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3
PARITY ENABLE
SEL OEBA OEAB
H
H
H
H
L
L
L
L
Inputs
xAPAR
H
H
H
H
L
L
L
L
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
H
xBPAR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Parity is checked on port A and is generated on port B.
Parity is checked on port B and is generated on port A.
Parity is checked on port B and port A.
Parity is generated on port A and B if device is in FF
mode.
Parity functions are
disabled; device acts as
a standard 18-bit
registered transceiver.
xAPAR
PO
PE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
INDUSTRIAL TEMPERATURE RANGE
L
L
L
L
(1)
(2)
Operation or Function
xERRA
H
H
H
H
H
H
H
H
L
L
Z
Z
Z
Z
L
L
Z
Z
Z
Z
L
L
L
L
Z
Z
Outputs
Q
Q
Q
Isolation
A
B
A
xBPAR
data to B, Q
data to A
data to B
PO
PE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
L
L
L
L
(1)
(2)
B
xERRB
data to A
H
H
H
H
H
H
H
H
Z
Z
Z
Z
L
L
Z
Z
Z
Z
L
L
L
L
L
L
Z
Z